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Christian Zietz schrieb:
> Without RAS/CAS the RAM chips won't drive the data bus; see the "read
> cycle" diagram in the datasheet you mentioned. However, due to the
> capacitance of the bus lines, these will keep their previous value for a
> short while.
Just to correct my e-mail from yesterday: I remembered that there is a
latch (74..373) between CPU data bus and RAM data bus. This latch is
under control of the MMU. So it's the latch that keeps the last data
word indefinitely when no RAM access is generated by the MMU -- no
parasitic capacitance needed.
I didn't check yesterday, but it's very probable that new data is only
latched when an access to a RAM bank is generated.
Christian Zietz - CHZ-Soft - czietz@xxxxxxx
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