|Re: [hatari-devel] test needed on a 4MB STF|
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Nicolas Pomarède schrieb:
> Does the STE has the same problem, or all the GST/MCU chips behave
> correctly with 2 distinct bank settings ?
As far as I know all GSTMCUs behave like the IMP ones in that regard,
i.e. they ignore the settings for bank1. This is confirmed at least on
my *STE* as nothing happens when I press F5 or F4 in your test program.
On the STE people also figured out that 2.5 MiB wouldn't work:
> Exactly, and that's what I can determine with these color patterns :)
> On my 1 MB STF, if I set bank1 to 128 K, then I can see that MAD8 (used
> as R8 on 512 K ram bank, but not used on 128 K bank) is set to the value
> of C0 (ie MAD0 when CAS values are sent first).
I've read though the material I have on ST MMUs. At least for the IMP
MMU it seems the following mapping happens -- for both banks equally:
During row addressing, the MMU doesn't even care about bank sizes:
A1 ... A10 -> RAS0 ... RAS9 (always)
During column addressing, the following happens:
A11 ... A20 -> CAS0 ... CAS9 (with 2 MiB),
A10 ... A18 -> CAS0 ... CAS8 (with 512 kiB),
A9 ... A16 -> CAS0 ... CAS7 (with 128 kiB).
This explains why you can see A9 on both RAS8 and CAS0 with 128 kiB
configuration. I'd have to recheck what happens to CAS8/CAS9 when 128
kiB or 512 kiB are set. Also, this could be different on the non-IMP MMU.
Christian Zietz - CHZ-Soft - czietz@xxxxxxx
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