|Re: [hatari-devel] Regression in 2.0.0 RC1|
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Le 27/10/2016 à 22:05, Christian Zietz a écrit :
Nicolas Pomarède schrieb:
- in one case, when repeat is not set, it seems dma stops when
start=end (or maybe it's just that dma doesn't start at all). DMA
address doesn't increase, else we would play RAM content one time.
- in the other case, when repeat is set and start=end too, then we see
the address increases and we play the RAM content.
So, does the schematic shows a different behaviour to increase DMA
address depending on whether repeat is set or not ? Why would DMA
address increase beyond end when repeat is set ?
What happens in the schematic when the DMA address counter (called SND,
there) hits the end address (SFT) depends on the "repeat flag" (SFREP):
If it is not set, this immediately sets a signal called STOFF, which in
turn resets the "enable flag" (SNDON) and stops the sound. STOFF is not
synchronized inside the GSTMCU, so this happens asynchronously with
respect to the clock -- more or less instantly. When the repeat flag is
set and the end address is reached, a signal called SFRAME is set
instead that triggers the reload of the start address (SFB) into the DMA
address counter. SFRAME, however, is synchronized to some clock (CLKB).
I don't know which that is.
Maybe -- and unfortunately I'm just hypothesizing here -- this
synchronization makes the counter reset fail when start == end and this
weird effect is exploited by the demo. If the counter would get
reloaded, it would always play the same sample over and over.
that's some open questions ;)
Indeed. Anyone, please feel free to interpret the schematic yourself,
it's ST4081S.PDF in the archive available on my website as I posted earlier.
Very interesting schematic, but unfortunatelly, I'm not very fluent at
ASIC reading :) For example on page 13, I see SNDON and SNDREP, but I
can't see where they're used on the other parts to fit with the
description you made above ?
Apart from that, here're some things that could be measured on STE :
- set start=end, start dma sound with repeat off : does dma turns off
immediately or at the end of the next video line where FIFO would be
Do we get the "end of frame" timer A interrupt in that case ?
I guess dma sound counter and bit 0 of ff8901 are updated at the end of
each line, when display enabled is set to off and shifter displays
- if start=end and we start dma sound with repeat on, do we also get
an immediate end of frame timer A interrupt, just before dma address
goes beyond end address ? As the end condition seems to not be correctly
checked in that case, maybe the end of frame bit in the MFP is not
available either and we would not get an input on timer A in event count