|Re: [hatari-devel] Regression in 2.0.0 RC1|
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Nicolas Pomarède schrieb:
> - in one case, when repeat is not set, it seems dma stops when
> start=end (or maybe it's just that dma doesn't start at all). DMA
> address doesn't increase, else we would play RAM content one time.
> - in the other case, when repeat is set and start=end too, then we see
> the address increases and we play the RAM content.
> So, does the schematic shows a different behaviour to increase DMA
> address depending on whether repeat is set or not ? Why would DMA
> address increase beyond end when repeat is set ?
What happens in the schematic when the DMA address counter (called SND,
there) hits the end address (SFT) depends on the "repeat flag" (SFREP):
If it is not set, this immediately sets a signal called STOFF, which in
turn resets the "enable flag" (SNDON) and stops the sound. STOFF is not
synchronized inside the GSTMCU, so this happens asynchronously with
respect to the clock -- more or less instantly. When the repeat flag is
set and the end address is reached, a signal called SFRAME is set
instead that triggers the reload of the start address (SFB) into the DMA
address counter. SFRAME, however, is synchronized to some clock (CLKB).
I don't know which that is.
Maybe -- and unfortunately I'm just hypothesizing here -- this
synchronization makes the counter reset fail when start == end and this
weird effect is exploited by the demo. If the counter would get
reloaded, it would always play the same sample over and over.
> that's some open questions ;)
Indeed. Anyone, please feel free to interpret the schematic yourself,
it's ST4081S.PDF in the archive available on my website as I posted earlier.
Anders Eriksson wrote:
> I realise this is pointing at me.
I didn't want to rush you to do anything. Also, surely there are other
people on this list who own an STE and can help?
Christian Zietz - CHZ-Soft - czietz@xxxxxxx
PGP/GnuPG-Key-ID: 0x52CB97F66DA025CA / 0x6DA025CA