Re: [hatari-devel] Adding cache support for the MegaSTE

[Christian Zietz <czietz@xxxxxxx>]

Christian Zietz schrieb:

> Results attached.

I struggle to understand the difference between 8 MHz and 16 MHz + 100% 
cache hits, though. The come out at $19E = 414 HBLs and $A7 = 167 HBLs, 
respectively, which is a 414/167 ≈ 2.5(!) speed increase.

You do a MOVE.W (Ax)+,Dx; DBRA Dy,xxx. The MOVE is 8 cycles, the DBRA is 
10 cycles. In 8 MHz mode the DBRA incurs two waitstates (because of 
unaligned prefetch from ST RAM). Hence, in 8 MHz mode the loop should 
take 8+10+2=20 cycles, equivalent to 40 16-MHz cycles.

Assuming 100% cache hit, in 16-MHz mode the same loop ought to take 8+10 
= 18 cycles.

But that only would explain a 2.22 (40/18) speed increase. I wonder if 
the rest is due to overhead in interrupt handling in 8-MHz mode.

Do you see a way to modify your test program to run with interrupts 
disabled, using, e.g., one of MFP timers for time measurement?

Regards
Christian
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