Re: [hatari-devel] New drive image settings

[Uwe Seimet <Uwe.Seimet@xxxxxxxxx>]

Hi,

I ran some tests with a real Falcon, and the result is: The Falcon's
sector count register seems to have a width of 16 bit. Actually, I never
cared much about this, because for HDDRIVER it's not relevant whether it's 8
or 16 bit as long as a value of 0 means 2^n, with n the number of supported
bits. Even 4 bit would work.

For Falcon SCSI HDDRIVER (to be more precise: the integrated SCSI Driver),
when more than 511 bytes have to be transferred takes the byte count
(32 bit value), shifts it 9 times to the right (dividing by 512) and writes
the low 16 bit of the result to the sector count register. The following DMA
transfer will transfer whatever the DMA chip is capable of doing with this
value. At the end of the transfer the SCSI Driver sets the DMA start address
to the current DMA end address.

That's it. Because HDDRIVER is target-driven what happens next depends
on the bus phase: If it's still DATA IN the next transfer will be started,
trying to transfer the remaining data. If it's not DATA IN anymore we
may either be done, or the target switched to a different bus phase
(e.g. for SCSI messaging). In practice there are devices that switch to a
different phase between transfers, indeed. Typically in case of slow
operations, where they want to temporarily disconnect. Not just streamers
or some hard disk drives during formatting. I once tested with a DVD-RAM
drive that requested a disconnect while reading data.

All in all, sooner or later any device will have transferred all data in
one or many DATA IN phases.
Note that from what I observed the Falcon's DMA chip reports an end
address that is 16 bytes too high if the DATA IN phase was interrupted
by a different phase, but the end address is correct if there was no
interruption.

I hope I did not miss anything, there was no need to closely look at this
code for almost 20 years.

Thomas, have you tried CBHD? As that's the only other driver that is
target-driven you might observe similar problems. But not necessarily,
because the DMA handling may be different and may limit each transfer to
255 blocks explicitly.

Best regards

Uwe