|Re: [hatari-devel] test needed on a 4MB STF|
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Le 22/12/2016 à 22:43, Christian Zietz a écrit :
Nicolas Pomarède schrieb:
I agree, not really needed for emulation too, but it's true that when
you nearly have a description of the inner working of this part of the
MMU, it would be nice to understand the reason and duplicate even the
strangest effect :)
I think I have now reverse-engineered how the access signals for the RAM
banks are generated for the Ricoh (aka non-IMP) MMU. Phey, I fear I'm
going to dream of logic gates and Boolean algebra tonight...
I can indeed see the "hole" for the bank0=128k, bank1=2M configuration.
No RAM access signals are generated for this configuration and A21..A18
= 0001, which is exactly the address range from $40000 to $7ffff. I'll
see if I can find some time during the holidays to transfer my
hand-written notes into some kind of documentation of my findings.
Good news, this might be useful too for other project like MIST or
similar which try to re-build a complete STF/STE with VHDL and require a
low level description of each chip.