Re: [hatari-devel] 68030 MMU emulation, TEMPLMON

[Andreas Grabher <andreas.grabher@xxxxxxxxxxxx>]

Am 16.10.2012 um 20:33 schrieb Uwe Seimet:

> Hi,
> 
>> Sorry for the late reply. I think you may have misunderstood the message.
>> 
>> PMOVE TT0,017E8107 PC=0041F1D0
>> 
>> for example means, that the value 0x017E8107 is moved to the TT0 register.
>> In the meantime the debugging output has been changed, so it should be more clear now.
> 
> I'm confused because according to the M68000PRM moving immediate values to
> the transparent translation registers is not supported by the 68030 i.e.
> 
> PMOVE TT0,017E8107 PC=0041F1D0
> 
> is not a legal instruction. My assembler (the Easy Rider assembler) also
> complains with "Adressierungsart nicht zugelassen" when I try
> 
>  pmove $017e8107,tt0
> 
> But
> 
>  pmove $017e8197,tc
> 
> works fine, and according to the PRM for the tc this addressing is legal,
> indeed.
> 
> The current debug output says
> 
> PMOVE: write TT0 017E8107
> 
> Either this is a misunderstandig on my side or something might still be
> wrong in the debug output?

Maybe i didn't clarify this: the debugging output does not reflect the actual assembler instruction. It just tells that something has been read from or written to TT0 and writes the values that has been read or written. It does not tell anything about the actual addressing mode.
Maybe this needs some improvement, but for my purpose it was just enough. I'm not aware of programming with assembler language, so i'd need some help with the syntax.

> 
> By the way, can you comment on my PRM (1st edition) reserving 6 bits for
> the MC68030 FC registers? In one of your previous emails you mentioned
> your copy says it's 5 bits, which is what I would have expected. Is
> there a newer edition of the PRM available somewhere?

I am using M68000PRM.pdf from:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68030&fpsp=1&tab=Documentation_Tab

In the manual i'm using the field for FC is only 4 bit wide (very strange that it is 6 in yours) and the register field is also 4 bit wide. I think the correct values are 3 bit for register (for A0 - A7) and 5 bit for the FC field. In the manual i'm using the PTEST opcode for 68030 is described on page 520 (6-66). On the next page the possible values for the FC field are described ... they are 5 bit wide (same as PLOAD and PFLUSH). I'm near 100 % sure that the datasheet is wrong and 5 bit are correct.
But if we want to confirm, someone could compile some different PTEST instructions and see what opcodes are in the binary.


> 
> Take care
> 
> Uwe
> 
>