Hi,
Please see section 8.2.1 in the MC68030 user's manual. I used a
different book:
https://www.abebooks.com/9780201088762/68030-Assembly-Language-Reference-Includes-0201088762/plp
when writing my PMMU-related tools. The faulted instruction in this case
may be anything that tried to write to a write-protected page, i.e. a
page write-protected for user mode writes based on its page descriptor.
The user's manual says:
If a rerun
bit is set when the processor executes an RTE instruction, the processor may
execute a bus cycle to prefetch the instruction word for the corresponding
stage of the pipe (if it is required). If the rerun and fault bits are set for a
stage of the pipe, the RTE instruction automatically reruns the prefetch cycle
for that stage. *The address space for the bus cycle is the program space for
the privilege level indicated in the copy of the status register on the stack.*
Best regards
Uwe
> > ---> It asks the CPU to retry the instruction that caused the bus error
> > in the first place in supervisor mode.
> > 0001ED10 BSET.B #$0002,(A7, $000b) == $00005707 [11]
> Ok, so this code sets SSW FC2 bit and then reruns faulted data access
> and CPU uses SSW FC mode to access the faulted data? Is this documented
> somewhere? I didn't find anything about CPU supporting modification of
> SSW FC bits.
>
> Current data fault restart part of emulation does not use modified SSW
> FC which probably explains the problem. Hopefully emulating this
> properly does not get too nasty... Other bits should be already emulated.
>
> btw, what is the actual faulted instruction?
>
>