On 28.01.2016 18:00, Nicolas Pomarède wrote:
Le 28/01/2016 17:05, Douglas Little a écrit :
Only polling is used. TimerC on CPU side is used for measuring MIPS
using fixed number of DSP operations - but the DSP communications are
all manually done via host port.
good, one less possible cause of trouble :)
I currently don't have time for checking ... but looking at the code in
m68k_run_2ce(), I basically see the following sequence:
(*cpufunctbl[r->opcode])(r->opcode);
wait_memory_cycles();
/* Flush all CE cycles so far to update PendingInterruptCount */
M68000_AddCycles_CE ( currcycle * 2 / CYCLE_UNIT );
currcycle = 0;
...
/* Run DSP 56k code if necessary */
if (bDspEnabled) {
DSP_Run(2 * currcycle * 2 / CYCLE_UNIT);
// DSP_Run ( DSP_CPU_FREQ_RATIO * ( (CyclesGlobalClockCounter - DSP_CyclesGlobalClockCounter) << nCpuFreqShift ) );
}
So isn't currcycle always 0 when DSP_Run is called? Sounds like either
the "currcycle = 0" should be done later, or the disabled, second
DSP_Run() should be used instead?
(but as I said, I currently don't have time for checking, so I
might be completely wrong here)