2010/8/18 joel falcou
<joel.falcou@xxxxxx>
On 18/08/10 17:07, Benoit Jacob wrote:
ah OK. I was naively hoping that alignment requirements wouldn't necessarily keep increasing with the packet size :-(
I was going to ask about that. Do you think this makes for a significant performance improvement for real-world dynamic-size matrices (size at least 32x32) ?
Next question: can't cache line size vary even within a particular architecture? Although that probably doesn't matter since I guess it'll always be bigger than any alignment _requirement_ (it'll be at least 64 bytes, right? which is bigger than any SIMD instructions require, right?)
It is my understanding that when x86 and x86-64 cpus come out with AVX instructions, people will want to generate executables that determine at runtime the availability of AVX, and switch between AVX and non-AVX code based on that. So ABI compatibility is going to be more important than ever. Right?
Well, I can comment as we don't support such use-case (new arch == new compilation)
For us too, new simd platform == new compilation, but we support the use case that consists in compiling the same code N times for N different SIMD configs, and switching between these N paths at runtime. This requires Eigen data structures to have the same ABI across different SIMD configs (i.e. SSE / no SSE), withing a given CPU arch (i.e. x86).
Benoit