Re: [eigen] about changeset 6eb14e380

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On 18/08/10 16:54, Benoit Jacob wrote:
Concretely, what are the future SIMD instruction sets that you are thinking about, that would have different alignment requirements? I've heard that AVX/LRB have wider packets, but do they also have bigger alignment requirements?
AVX require 256 bits alignement and have 256 bits packets. Gael approach is the oen we had in NT2

So the only worrisome thing is a single CPU architecture that could have multiple SIMD instruction sets, with different alignment requirements.

In any case, if you have 2 ISA : one requiring 2^N and other 2^M, aligning on the biggest is enough as.

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