| Re: [eigen] about changeset 6eb14e380 |
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On 18/08/10 17:21, Benoit Jacob wrote:
I was going to ask about that. Do you think this makes for a
significant performance improvement for real-world dynamic-size
matrices (size at least 32x32) ?
For us it is useful to prevent false sharing on same row/col in openMP
scenario.
Next question: can't cache line size vary even within a particular
architecture? Although that probably doesn't matter since I guess
it'll always be bigger than any alignment _requirement_ (it'll be at
least 64 bytes, right? which is bigger than any SIMD instructions
require, right?)
It varies yes. NT2 instalaltion detect it and put it into a
NT2_CONFIG_ALIGNMENT macro to be used.
For us too, new simd platform == new compilation, but we support the
use case that consists in compiling the same code N times for N
different SIMD configs, and switching between these N paths at
runtime. This requires Eigen data structures to have the same ABI
across different SIMD configs (i.e. SSE / no SSE), withing a given CPU
arch (i.e. x86).
Ah yes then.