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- To: eigen@xxxxxxxxxxxxxxxxxxx
- Subject: Re: [eigen] about changeset 6eb14e380
- From: Benoit Jacob <jacob.benoit.1@xxxxxxxxx>
- Date: Wed, 18 Aug 2010 11:07:34 -0400
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2010/8/18 joel falcou <joel.falcou@xxxxxx>
AVX require 256 bits alignement and have 256 bits packets. Gael approach is the oen we had in NT2
On 18/08/10 16:54, Benoit Jacob wrote:
Concretely, what are the future SIMD instruction sets that you are thinking about, that would have different alignment requirements? I've heard that AVX/LRB have wider packets, but do they also have bigger alignment requirements?
ah OK. I was naively hoping that alignment requirements wouldn't necessarily keep increasing with the packet size :-(
In any case, if you have 2 ISA : one requiring 2^N and other 2^M, aligning on the biggest is enough as.
So the only worrisome thing is a single CPU architecture that could have multiple SIMD instruction sets, with different alignment requirements.
This sure is feasible for head-allocated matrices.. But what do you do for fixed-size matrices?
If we can rely on the assumption that alignment_requirement == packet_size then we could align fixed-size matrices to the biggest useful alignment that doesn't increase their sizeof() and remember that as compile-time information. Then, when emitting SIMD instructions, we'd be checking that the alignment is enough for the SIMD instruction set in use, etc. Gael, does that sound OK?
The advantage of that approach is that, since it still never increases the sizeof(), it can still be done exactly in the same way when vectorization is disabled, so we keep ABI compatibility.
It is my understanding that when x86 and x86-64 cpus come out with AVX instructions, people will want to generate executables that determine at runtime the availability of AVX, and switch between AVX and non-AVX code based on that. So ABI compatibility is going to be more important than ever. Right?