Re: [hatari-devel] Dynamic Bus Sizing and I/O Register Access

[Toni Wilen <twilen@xxxxxxxxxx>]

>Thank you Toni! Can you point me to the place in WinUAE where this is handled (if Amiga has any such case)?

>Maybe I am able to understand this by reading the code. The description in the data sheet is confusing me.

Don't have any examples now but the device seems to be designed to only have 32-bit wide registers and bits 0 and 1 of address bus are not connected (or most likely don't even exist to save pins).  CPU sees it as 32-bit device, I don't think this case needs bus sizing needed (no need to split the access)

This is feels somewhat similar to Amiga and 53C710 (and later) SCSI chips that only have 32-bit registers but some drivers still use byte reads to check some status bits. Nothing special is needed, except endian-swapping. (which in case of reading bytes means address 3 becoming address 0, 2 becomes 1 and so on)

More details needed. (chip type, register that is read using both byte and long -wide instructions, exact instructions used)