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10.2.5.2
HI Interrupts Host Request (HREQ)
The host processor interrupts are external and use the HREQ pin. HREQ is
normally con-
nected to the host processor maskable interrupt (IPL0 or IPL1 or IPL2 in
Figure 10-16)
input. The host processor acknowledges host interrupts by executing an
interrupt service
routine. The most significant bit (HREQ) of the ISR may be tested by the
host processor
to determine if the DSP is the interrupting device and the two least
significant bits (RXDF
and TXDE) may be tested to determine the interrupt source (see Figure
10-17). The host
processor interrupt service routine must read or write the appropriate
HI register to clear
the interrupt. HREQ is deasserted when1) the enabled request is cleared
or masked, 2)
DMA HACK is asserted, or 3) the DSP is reset.