| Re: [chrony-users] Time offset on versions 3+ without hw timestamping |
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William G. Unruh __| Canadian Institute for|____ Tel: +1(604)822-3273
Physics&Astronomy _|___ Advanced Research _|____ Fax: +1(604)822-5324
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On Wed, 11 Oct 2017, Miroslav Lichvar wrote:
On Wed, Oct 11, 2017 at 06:26:51PM +0200, Thibaut BEYLER wrote:
Thanks, that seems like an interesting solution for power-saving. So far i
disabled c-state and power management system-wide (
using /dev/cpu_dma_latency and governors) which gives really good results
(more stable peer delay & std dev)
My PPS stddev get under 500ns, I however still get a constant offset betwen
my PPS source and my ntp sources of about 8-9us (same with different PPS
sources)
Even if the CPU never enters a power-saving mode, I think there will
always be some delay between the interrupt and the kernel actually
making a PPS timestamp.
That should be of the order of a usec, not 8 or 9. On the otherhand one way
network delays of 8 or 9 us are very possible. It I would blame the ntp
network timestamping not the PPS. What is the network path to the ntp source?
Also does the pps source also trigger some other IRQ server. That other program could easily take 8-9usec
to process and delay your pps servicing.
If the delay is stable and known, the measurements can be fixed with
the offset option.
A polling driver might be able to provide a better accuracy. I'm using
this one on a AR93xx-based board: https://github.com/mlichvar/pps-gpio-poll
Another way to get a sub-microsecond accuracy might be with the i210
card. It has software defined pins (SDP), which can be used for
external timestamping of a PPS signal. The extpps option of the PPS
refclock in chrony enables that.
I really don't think it's a problem on the ntp servers side as it's using
two asic-powered sources with hardware timestamping, get constant stddev
under 10ns and can get value like 1.28us for "peer delay" and "max. error"
under 4us when i bypass the switch (for testing purpose)
But how does the ntp signal get from the ntp server to the computer? That path
might have one-way delays in it.
I guess there is still some delay somewhere on the PPS signal processing
that gives this offset.
It is hard to imagine that giving 8-9us unless you are using an 8088 computer.
Most irq time handlers will grab the system time first thing when called.
Thus it is the irq handling time in the cpu that gives the time delay.
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