Re: [hatari-devel] TT hardware memory information

[Thomas Huth <th.huth@xxxxxx>]

Am Wed, 16 Mar 2016 17:25:16 -0600 (MDT)
schrieb David Savinkoff <dsavnkff@xxxxxxxxx>:

> ----- Thomas Huth wrote:
> > On 16.03.2016 02:10, Roger Burrows wrote:  
> > > The TT has a sync mode register at the same address as the ST
> > > (0xff820a). However, it's not set up the same way.  TOS3
> > > initialises it to 0x01 very early in initialisation, and it is
> > > not updated elsewhere.  While getting EmuTOS working on my TT, I
> > > discovered that, if this is set to 0x00 or 0x02 (like it would be
> > > on an ST), there is NO output to the screen: my LCD monitor
> > > remains blank, although it does detect the correct screen size
> > > and refresh rate.  
> 
> I think the TT is doing exactly what you said:
> The TT puts out a black picture (blanked) with hsync an vsync running
> as usual. Thus, if you want a black screen you zero the bit.

What should be the purpose of that? To get a black screen, you could
also simply set the palette to zero.

> This should be tested because I'm sure a demo will be made, if it
> isn't already.

Who's going to do that? And why?

> > > In the "Atari TT030 Hardware Reference Manual", June 1990, there
> > > is a note that bit 0 of this register is 'set to 1'.  There is no
> > > further explanation.  
> > 
> > IIRC, I once read somewhere that bit 0 of this register has been
> > inverted on the TT, i.e. when it is set to 0, that means the sync
> > signals are taken from external source, and 1 means that they are
> > generated from the shifter.  
> 
> I looked at the schematics and could find no means to accept hsync or
> vsync or any video signal from an external source. Can it be done?

I never looked into that external synchronization stuff before, but at
least on the STE, it seems like it was possible, according to:
ftp://untergrund.net/users/ggn/Atari%20HQ/Documents/Atari/TECHDOCS/STE/FSG/STE_CH2.TXT

"2.11  GENLOCK AND THE STE

 The ST (and STE) chip set have the ability to accept external sync. This is controlled by bit
 0  at FF820A, as documented in the ST Hardware Specification. This is provided to allow the
 synchronization of the ST video. In order to do this reliably the system clock must also be
 phase-locked (or synchronized in some other way) to the input sync signals. No way to achieve
 this was provided in the ST. As a result, the only GENLOCKs available were internal
 modifications (usually for the MEGA).
 The STE, on the other hand, allows this to be done without opening the case. To inject a system
 clock ground pin three (GPO) on the monitor connector and then inject the clock into pin 4
 (mono detect)."

So I assume it was either similar on the TT like on the STE, or you
needed a further hardware modification like on the ST.

 Thomas