Re: [hatari-devel] CPU <-> DSP timing issue in Voxel demo?

[Douglas Little <doug694@xxxxxxxxxxxxxx>]

Hi,

When I profiled the CPU side code, I noticed something strange:
-----------------------------------------------------------------
Data cache hits per instruction, number of occurrencies:
  0: ################################################## 99.677%
  1: # 0.271%
  2: # 0.036%


Data cache misses per instruction, number of occurrencies:
  0: ################################################## 99.708%
  1: # 0.231%
  2: # 0.052%

 

I'd tend to agree. That looks very strange to me also..

d-cache hit rate is typically very low unless 'arranged' by the code - very algorithm-dependent. I wouldn't expect to see much higher than 50% with less than ideal circumstances.

D.