I have another question about the DSP code. The CPU needs to interrupt the DSP using IRQB.
I looked at the available interrupt vectors in dsp_core.h:
#define DSP_INTER_RESET 0x0
#define DSP_INTER_ILLEGAL 0x1
#define DSP_INTER_STACK_ERROR 0x2
#define DSP_INTER_TRACE 0x3
#define DSP_INTER_SWI 0x4
#define DSP_INTER_HOST_COMMAND 0x5
#define DSP_INTER_HOST_RCV_DATA 0x6
#define DSP_INTER_HOST_TRX_DATA 0x7
#define DSP_INTER_SSI_RCV_DATA_E 0x8
#define DSP_INTER_SSI_RCV_DATA 0x9
#define DSP_INTER_SSI_TRX_DATA_E 0xa
#define DSP_INTER_SSI_TRX_DATA 0xb
If does not match the on from the data sheet (DSP56000/560001UM rev2, see appended file):
0x0000: Hardware RESET
0x0002: Stack error
What might be the reason for this? Mistake or intentional difference?
<interrupt sources.png> <dsp_patch3.diff>
Luckily it turned out that the mode bits in the system control register are inverted. So mode 2 is mode 1 and that is the one that is implemented.
With some additions to the code (some bits in ICR seemed to be ignored) now at least it does something.
Maybe some of these changes are useful for Hatari too (see appended file). I'd be glad if someone could check them for correctness.
btw. It seems to me that Hatari is releasing the HREQ interrupt in a wrong way. DSP should release it, not CPU.