Re: [hatari-devel] DSP bug: need more explanations

[Laurent Sallafranque <laurent.sallafranque@xxxxxxx>]

Hi,

Thanks a lot for the reply, this makes sense.
I've got an idea to fix this bug once for all.

But it'll be after the chrismas hollydays ;)

Laurent



Le 22/12/2014 09:04, Miro Kropáček a écrit :

On Mon, Dec 22, 2014 at 1:21 AM, Laurent Sallafranque <laurent.sallafranque@xxxxxxx> wrote:

Note: This instruction is considered to be a move-type instruction. Due to pipelining, the
new contents of the destination address register (R0–R7 or N0–N7) will not be available
for use during the following instruction (i.e., there is a single instruction cycle pipeline
delay).

What I *think* is meant here that it is not available for next instruction when calculating another EA. Simplified:

move a,n0

move n0,b

is perfectly legal while

move a,n0

move x:(r0+n0),b

is not.

So you're OK to write

lua (r0)+n0,n1

move n1,b ; updated n1 here

but not

lua (r0)+n0,n1

move x:(r1+n1),x0 ; using old n1 here

The pipelining problem is about EA calculation, not instruction ordering.

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