Re: [hatari-devel] DSP bug: need more explanations

[Laurent Sallafranque <laurent.sallafranque@xxxxxxx>]

here it is :


diff -r c84704b8581a CMakeLists.txt
--- a/CMakeLists.txt	Sat Dec 20 01:10:59 2014 +0200
+++ b/CMakeLists.txt	Sun Dec 21 22:27:51 2014 +0100
@@ -38,7 +38,7 @@
     CACHE BOOL "Enable tracing messages for debugging")
 set(ENABLE_SMALL_MEM 0
     CACHE BOOL "Enable to use less memory - at the expense of emulation speed")
-set(ENABLE_WINUAE_CPU 0
+set(ENABLE_WINUAE_CPU 1
     CACHE BOOL "Enable WinUAE CPU core (experimental!)")
 
 # Run-time checks with GCC "mudflap" etc features:
diff -r c84704b8581a src/falcon/dsp_core.c
--- a/src/falcon/dsp_core.c	Sat Dec 20 01:10:59 2014 +0200
+++ b/src/falcon/dsp_core.c	Sun Dec 21 22:27:51 2014 +0100
@@ -195,6 +195,13 @@
 	/* Misc */
 	dsp_core.loop_rep = 0;
 
+	/* Rx, Nx and Mx pipeline reset */
+	dsp_core.pipe0_reg = 0;
+	dsp_core.pipe0_reg_value = 0;
+	dsp_core.pipe1_reg = 0;
+	dsp_core.pipe1_reg_value = 0;
+	dsp_core.allow_reg_trace = 0;
+
 	LOG_TRACE(TRACE_DSP_STATE, "Dsp: reset done\n");
 	dsp56k_init_cpu();
 }
diff -r c84704b8581a src/falcon/dsp_core.h
--- a/src/falcon/dsp_core.h	Sat Dec 20 01:10:59 2014 +0200
+++ b/src/falcon/dsp_core.h	Sun Dec 21 22:27:51 2014 +0100
@@ -238,6 +238,13 @@
 	Uint16  interrupt_pipeline_count;	/* used to prefetch correctly the 2 inter instructions */
 	Sint16  interrupt_ipl[12];		/* store the current IPL for each interrupt */
 	Uint16  interrupt_isPending[12];	/* store if interrupt is pending for each interrupt */
+
+	/* Rx, Nx and Mx pipeline */
+	Uint32	pipe0_reg;			/* Used to delay the Rx, Nx or Mx registers by one instruction */
+	Uint32	pipe0_reg_value;		/* Used to delay the Rx, Nx or Mx registers by one instruction */
+	Uint32	pipe1_reg;			/* Used to delay the Rx, Nx or Mx registers by one instruction */
+	Uint32	pipe1_reg_value;		/* Used to delay the Rx, Nx or Mx registers by one instruction */
+	Uint32	allow_reg_trace;
 };
 
 
diff -r c84704b8581a src/falcon/dsp_cpu.c
--- a/src/falcon/dsp_cpu.c	Sat Dec 20 01:10:59 2014 +0200
+++ b/src/falcon/dsp_cpu.c	Sun Dec 21 22:27:51 2014 +0100
@@ -829,6 +829,24 @@
 	/* Process Interrupts */
 	dsp_postexecute_interrupts();
 
+	/* Manage the registers R N M pipeline */
+//	if (dsp_core.allow_reg_trace == 1) {
+//		DSP_DisasmRegisters();
+//		dsp_core.allow_reg_trace++;
+//	}
+
+	if (dsp_core.pipe0_reg != 0) {
+		dsp_core.registers[dsp_core.pipe0_reg] = dsp_core.pipe0_reg_value;
+//		fprintf(stderr, "PIP: %d %d (pc=%04x)\n",  dsp_core.pipe0_reg, dsp_core.pipe0_reg_value, dsp_core.pc);
+//		DSP_DisasmRegisters();
+//		fprintf(stderr, "\n"),
+//		dsp_core.allow_reg_trace = 0;
+	}
+	dsp_core.pipe0_reg = dsp_core.pipe1_reg;
+	dsp_core.pipe0_reg_value = dsp_core.pipe1_reg_value;
+	dsp_core.pipe1_reg = 0;
+
+
 #if DSP_COUNT_IPS
 	++num_inst;
 	if ((num_inst & 63) == 0) {
@@ -1816,6 +1834,7 @@
 		cur_inst_len = 0;
 		fprintf(stderr, "Dsp: 0x%04x: 0x%06x Illegal instruction\n",dsp_core.pc, cur_inst);
 		/* Add some artificial CPU cycles to avoid being stuck in an infinite loop */
+		DebugUI(REASON_DSP_EXCEPTION);
 		dsp_core.instr_cycle += 100;
 	}
 	else {
@@ -2871,10 +2890,17 @@
 	dstreg = cur_inst & BITMASK(3);
 
 	if (cur_inst & (1<<3)) {
-		dsp_core.registers[DSP_REG_N0+dstreg] = srcnew;
+		dsp_core.pipe1_reg = DSP_REG_N0+dstreg;
+		dsp_core.pipe1_reg_value = srcnew;
 	} else {
-		dsp_core.registers[DSP_REG_R0+dstreg] = srcnew;
-	}
+		dsp_core.pipe1_reg = DSP_REG_R0+dstreg;
+		dsp_core.pipe1_reg_value = srcnew;
+	}
+
+//	fprintf(stderr, "\n"),
+//	fprintf(stderr, "LUA: %d %d (pc=%04x)\n",  dsp_core.pipe1_reg, dsp_core.pipe1_reg_value, dsp_core.pc);
+//	DSP_DisasmRegisters();
+//	dsp_core.allow_reg_trace = 1;
 
 	dsp_core.instr_cycle += 2;
 }