|Re: [hatari-devel] Code execution discontinuities and detecting them?|
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Interrupts are quite easy to detect in the DSP, as the first $40
locations of DSP56001 on-chip P:memory are used for interrupt vectors.
(These adresses work 2 by 2)
P:$0000 3 Hardware RESET (External)
P:$0002 3 Stack Error
P:$0004 3 Trace
P:$0006 3 SWI (Software Interrupt)
P:$003C 0-2 Available for Host Command
P:$003E P:$0000 or P:$E000 0-2 Illegal Instruction
When a program interrupts, the PC goes to one of these location (eg
:$002E and P:$002F),
So there's no separate exception handler invocation instruction,
like TRAP on m68k?
There's only the vector table at the beginning of the P: memory
does execute the 1 or 2 instructions there and then
returns to the original code.
Do you mean that exception handler can be only 1-2 instructions...?
No, the DSP PC will run to the vector address as described in the
previous mail, and execute the 1 or 2 instructions there (2 if each
instruction is 1 DSP word size, one else).
One of these 2 instructions can be a JSR, ... and the PC will continue
until it reachs a RTI.
Vector $26 contains (that's wrong, of course, as the JSR is a 2 word
instruction because of the jump address, but it's just for the example)
P:$0026 JSR $2000
; We're starting here in the main program
Interrupt here at vector $26
P:$0026 JSR P:$02000 ; Jump to the interruption subroutine
P:$2000 ADD X1,Y1
P:$2001 RTI ; end of the interruption subroutine
P:$0027 NOP ; second vector interrupt
P:$1003 NOP ; main program again
Careful, if the first instruction is a jump, the PC may not go to the
second vector address
...or just that the code can be elsewhere? :-)
Yes, it can be elsewhere, or directly in the 2 words addresses directly
into the vector.
Is RTI instruction involved in both cases?
Can there be exceptions within exception handler, and
in which case RTI returns just to previous handler?
? Sorry, I don't understand what you're asking here.