Re: [hatari-devel] DSP question

[Laurent Sallafranque <laurent.sallafranque@xxxxxxx>]

I'm not sure to understand correctly the problem (if there's one).

I don't know what you're testing, so I try to guess.

You write a first value into the DSP host ---> to the 68030
Then you write a second one (this one shouldn't be writen into the internal HI register as long as the 68030 has read the first one) ...

Maybe if you have a little test program that I could run on my falcon we could verify if there's a problem ?

Regards
Laurent


Le 26/02/2013 19:33, Douglas Little a écrit :

Hi,

In the DSP HostPort, there are 2 independant registers : 1 for host -> dsp and one for DSP -> host exchanges.

Yes this part I knew about.

 

It's not really a FIFO but I would call it a buffer.
You can write the second value you want to send to the 68030 while it gets the first one.

I suppose the behaviour seen can be interpreted differently from the way the HW is implemented - the host port register itself is a kind of buffer (in the sense that it holds state separately from the CPU and DSP), and if there is an additional internal buffer, that's 2 levels of buffering already - writing a 3rd value would cause the pipe to block (which is exactly what I'm seeing).

However if the host port register itself is the *only* buffer, and there is no additional internal buffer, it would not reflect what I am seeing.

To be clear, I'm seeing 2 levels of decoupling between the processors - in a single direction. Not just a single level, as would be expected from the 'register' on its own.

To be noticed : in the 68030 --> DSP exchange, there's also a burst mode I've implemented (I just don't know if the timings are correct here).

I don't know anything about this part. Do you have some reference I can look at?

 

Thanks,

D.