Re: [hatari-devel] DSP question

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Hi,

I've coded this part as described in the DSP manual.
Without it, many demos didn't work properly.

In the DSP HostPort, there are 2 independant registers : 1 for host -> dsp and one for DSP -> host exchanges.

It's not really a FIFO but I would call it a buffer.
You can write the second value you want to send to the 68030 while it gets the first one.

To be noticed : in the 68030 --> DSP exchange, there's also a burst mode I've implemented (I just don't know if the timings are correct here).

Regards

Laurent



Le 26/02/2013 16:47, Douglas Little a écrit :
I have a Hatari DSP question now. Perhaps one for Laurent but I'd be interested if anyone knows the answer to this one.

I've been looking at concurrency behaviour in my program relating to DSP host port events - points where CPU and DSP synchronize briefly and make some data exchanges.

It appears the DSP isn't being held up (blocking/spinning) at the exchange points I expected - rather 2 exchanges farther on than expected. It behaves exactly as I'd expect if the host port was decoupled via a 2-deep FIFO in at least one direction - probably both directions. (i.e. the DSP can write 2 values to the host port without the CPU doing anything, but the 3rd would block until the 1st is retrieved).

Is this actually how the host port is implemented in Hatari? And if so, is it the same situation on real hardware? It's interesting because it has (good) implications for performance if used properly. But I'd like to confirm it before relying on anything like that.

(It wouldn't be surprising to me if there is a FIFO present - but knowing for sure and the actual depth is very interesting).

D.




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