| Re: [hatari-devel] 68030 MMU emulation, TEMPLMON |
[ Thread Index |
Date Index
| More lists.tuxfamily.org/hatari-devel Archives
]
Am 17.10.2012 um 18:58 schrieb Roger Burrows:
> On 17 Oct 2012 at 18:14, Andreas Grabher wrote:
>> Am 16.10.2012 um 20:33 schrieb Uwe Seimet:
>>>
>>> By the way, can you comment on my PRM (1st edition) reserving 6 bits for
>>> the MC68030 FC registers? In one of your previous emails you mentioned
>>> your copy says it's 5 bits, which is what I would have expected. Is
>>> there a newer edition of the PRM available somewhere?
>>
>> I am using M68000PRM.pdf from:
>> http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MC68030&fpsp=1&;
>> tab=Documentation_Tab
>>
>> In the manual i'm using the field for FC is only 4 bit wide (very strange that
>> it is 6 in yours) and the register field is also 4 bit wide. I think the
>> correct values are 3 bit for register (for A0 - A7) and 5 bit for the FC
>> field. In the manual i'm using the PTEST opcode for 68030 is described on page
>> 520 (6-66). On the next page the possible values for the FC field are
>> described ... they are 5 bit wide (same as PLOAD and PFLUSH). I'm near 100 %
>> sure that the datasheet is wrong and 5 bit are correct.
>> But if we want to confirm, someone could compile some different PTEST
>> instructions and see what opcodes are in the binary.
>>
>
> I have the PRM in hardcopy - on the last page it says printed 2/97.
>
> The last byte of the PTEST instruction (shown on page 6-66) has bits 7-5 for
> register, bits 4-0 for FC.
>
> Roger
>
>
Great! That is exactly what is implemented in the PTEST emulation.
It confirms my guess.
>