| [AD] More AMD64 stuff |
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(hmm... send this too the wrong list first it seems...) Good stuff this time :) The attached patch makes the configure script recognize the AMD64 as a processor type, and it adds a hook for allowing AMD64 optimized assembler code. It also adds an ALLEGRO_AMD64 preprocessor symbol. This portion of the patch is IMO certainly clean enough for 4.2. The next part I think as well, but I want a second opinion here. Currently, the only thing this is used for is to port over the CPU identification code. This seems to work like a charm, but I'm not too comfortable with the way I had to grab the arguments passed to the function: %rdi gets the first argument, %rsi gets the second one. I did some googling and checking around and this does seem to be normal (and it certainly simplifies the code significantly), but I'd like to hear more opinions on it. It should be possible to port over the existing assembler code in a fairly generic way, but I don't think that's worthwhile: the 64 bit output from gcc is probably better than the hacked-ported code that would result from the i386 code. The patch also includes an improved version of my previous patch for the test programme so that it displays "CPU family: AMD64 / a hole range of capabilities". Evert
? src/amd64
Index: aclocal.m4
===================================================================
RCS file: /cvsroot/alleg/allegro/aclocal.m4,v
retrieving revision 1.73
diff -u -r1.73 aclocal.m4
--- aclocal.m4 13 Dec 2004 11:14:58 -0000 1.73
+++ aclocal.m4 7 Mar 2005 10:26:51 -0000
@@ -29,7 +29,17 @@
" ret\n"
" restore" : :)],
allegro_cv_processor_type=sparc,
-allegro_cv_processor_type=unknown))])
+AC_TRY_COMPILE([], [asm (".globl _dummy_function\n"
+"_dummy_function:\n"
+" pushq %%rbp\n"
+" movl %%esp, %%ebp\n"
+" leal 10(%%ebx, %%ecx, 4), %%edx\n"
+" callq *%%rdx\n"
+" addl %%ebx, %%eax\n"
+" popq %%rbp\n"
+" ret" : :)],
+allegro_cv_processor_type=amd64,
+allegro_cv_processor_type=unknown)))])
AC_MSG_RESULT($allegro_cv_processor_type)])
dnl
@@ -780,3 +790,23 @@
])
CFLAGS="$allegro_save_CFLAGS"
AC_MSG_RESULT($allegro_cv_support_i386_mtune)])
+
+dnl
+dnl Test for working '-mtune' amd64 compile option.
+dnl
+dnl Variables:
+dnl allegro_cv_support_amd64_mtune=(yes|no)
+dnl
+AC_DEFUN(ALLEGRO_ACTEST_GCC_AMD64_MTUNE,
+[AC_MSG_CHECKING(whether -mtune is supported)
+allegro_save_CFLAGS="$CFLAGS"
+CFLAGS="-mtune=athlon64"
+AC_CACHE_VAL(allegro_cv_support_amd64_mtune,
+[if test $GCC = yes; then
+ AC_TRY_COMPILE(,int foo(){return 0;}, allegro_cv_support_amd64_mtune=yes, allegro_cv_support_amd64_mtune=no)
+else
+ allegro_cv_support_amd64_mtune=no
+fi
+])
+CFLAGS="$allegro_save_CFLAGS"
+AC_MSG_RESULT($allegro_cv_support_amd64_mtune)])
Index: configure.in
===================================================================
RCS file: /cvsroot/alleg/allegro/configure.in,v
retrieving revision 1.85
diff -u -r1.85 configure.in
--- configure.in 27 Sep 2004 16:49:22 -0000 1.85
+++ configure.in 7 Mar 2005 10:26:51 -0000
@@ -154,6 +154,11 @@
ALLEGRO_ACTEST_GCC_I386_MTUNE
fi
+dnl Test for -mtune AMD64 option
+if test "X$allegro_cv_processor_type" = "Xamd64"; then
+ ALLEGRO_ACTEST_GCC_AMD64_MTUNE
+fi
+
dnl Test for asm support.
if test "X$allegro_enable_asm" = "Xyes"; then
if test "X$allegro_cv_processor_type" = "Xi386"; then
@@ -173,6 +178,17 @@
AC_DEFINE(ALLEGRO_SSE,1,[Define if assembler supports SSE.])
_code_features="$_code_features, SSE"
fi
+ elif test "X$allegro_cv_processor_type" = "Xamd64"; then
+ ALLEGRO_MAYBE_ASM_FILES=ALLEGRO_SRC_AMD64_FILES
+ _code_features="amd64 asm"
+
+ dnl MMX support available if AMD64 is available, but we can't use it yet.
+ dnl AC_DEFINE(ALLEGRO_MMX,1,[Define if assembler supports MMX.])
+ dnl _code_features="$_code_features, MMX"
+
+ dnl SSE support available if AMD64 is available, but we can't use it yet.
+ dnl AC_DEFINE(ALLEGRO_SSE,1,[Define if assembler supports SSE.])
+ dnl _code_features="$_code_features, SSE"
fi
fi
@@ -702,6 +718,18 @@
else
TARGET_ARCH="-mcpu=$allegro_optimizations"
fi
+ elif test "X$allegro_cv_processor_type" = "Xamd64"; then
+ dnl Change default pentium->athlon64
+ if test "X$allegro_optimizations" = "Xpentium"; then
+ allegro_optimizations="athlon64"
+ fi
+ if test "$allegro_exclusive_optimizations" != none; then
+ TARGET_ARCH="-march=$allegro_exclusive_optimizations"
+ elif test "X$allegro_cv_support_amd64_mtune" = "Xyes"; then
+ TARGET_ARCH="-mtune=$allegro_optimizations"
+ else
+ TARGET_ARCH="-mcpu=$allegro_optimizations"
+ fi
else
TARGET_ARCH=
fi
Index: makefile.lst
===================================================================
RCS file: /cvsroot/alleg/allegro/makefile.lst,v
retrieving revision 1.108
diff -u -r1.108 makefile.lst
--- makefile.lst 25 Jan 2005 14:25:54 -0000 1.108
+++ makefile.lst 7 Mar 2005 10:26:52 -0000
@@ -123,6 +123,38 @@
src/i386/izbuf.s \
src/misc/icolconv.s
+ALLEGRO_SRC_AMD64_FILES = \
+ src/c/cblit16.c \
+ src/c/cblit24.c \
+ src/c/cblit32.c \
+ src/c/cblit8.c \
+ src/i386/icpu.c \
+ src/amd64/acpus.s \
+ src/c/ccsprite.c \
+ src/c/cgfx15.c \
+ src/c/cgfx16.c \
+ src/c/cgfx24.c \
+ src/c/cgfx32.c \
+ src/c/cgfx8.c \
+ src/c/cmisc.c \
+ src/c/cscan15.c \
+ src/c/cscan16.c \
+ src/c/cscan24.c \
+ src/c/cscan32.c \
+ src/c/cscan8.c \
+ src/c/cspr15.c \
+ src/c/cspr16.c \
+ src/c/cspr24.c \
+ src/c/cspr32.c \
+ src/c/cspr8.c \
+ src/c/cstretch.c \
+ src/c/czscan15.c \
+ src/c/czscan16.c \
+ src/c/czscan24.c \
+ src/c/czscan32.c \
+ src/c/czscan8.c \
+ src/misc/ccolconv.c
+
ALLEGRO_SRC_DOS_FILES = \
src/dos/adlib.c \
src/dos/awedata.c \
Index: include/allegro/internal/alconfig.h
===================================================================
RCS file: /cvsroot/alleg/allegro/include/allegro/internal/alconfig.h,v
retrieving revision 1.16
diff -u -r1.16 alconfig.h
--- include/allegro/internal/alconfig.h 1 Feb 2005 13:12:05 -0000 1.16
+++ include/allegro/internal/alconfig.h 7 Mar 2005 10:26:52 -0000
@@ -112,6 +112,11 @@
#define _AL_SINCOS(x, s, c) __asm__ ("fsincos" : "=t" (c), "=u" (s) : "0" (x))
#endif
+ #ifdef __amd64__
+ #define ALLEGRO_AMD64
+ #define _AL_SINCOS(x, s, c) __asm__ ("fsincos" : "=t" (c), "=u" (s) : "0" (x))
+ #endif
+
#ifndef AL_CONST
#define AL_CONST const
#endif
Index: src/i386/asmdef.c
===================================================================
RCS file: /cvsroot/alleg/allegro/src/i386/asmdef.c,v
retrieving revision 1.21
diff -u -r1.21 asmdef.c
--- src/i386/asmdef.c 5 Aug 2004 15:41:22 -0000 1.21
+++ src/i386/asmdef.c 7 Mar 2005 10:26:54 -0000
@@ -36,7 +36,7 @@
typedef struct {
char *name;
- int value;
+ uintptr_t value;
}offset_entry_t;
offset_entry_t list[] = {
@@ -88,23 +88,23 @@
#ifdef ALLEGRO_NO_ASM
{"##ALLEGRO_NO_ASM", 0},
#endif
- {"BMP_W", (int)offsetof(BITMAP, w)},
- {"BMP_H", (int)offsetof(BITMAP, h)},
- {"BMP_CLIP", (int)offsetof(BITMAP, clip)},
- {"BMP_CL", (int)offsetof(BITMAP, cl)},
- {"BMP_CR", (int)offsetof(BITMAP, cr)},
- {"BMP_CT", (int)offsetof(BITMAP, ct)},
- {"BMP_CB", (int)offsetof(BITMAP, cb)},
- {"BMP_VTABLE", (int)offsetof(BITMAP, vtable)},
- {"BMP_WBANK", (int)offsetof(BITMAP, write_bank)},
- {"BMP_RBANK", (int)offsetof(BITMAP, read_bank)},
- {"BMP_DAT", (int)offsetof(BITMAP, dat)},
- {"BMP_ID", (int)offsetof(BITMAP, id)},
- {"BMP_EXTRA", (int)offsetof(BITMAP, extra)},
- {"BMP_XOFFSET",(int)offsetof(BITMAP, x_ofs)},
- {"BMP_YOFFSET",(int)offsetof(BITMAP, y_ofs)},
- {"BMP_SEG", (int)offsetof(BITMAP, seg)},
- {"BMP_LINE", (int)offsetof(BITMAP, line)},
+ {"BMP_W", (uintptr_t)offsetof(BITMAP, w)},
+ {"BMP_H", (uintptr_t)offsetof(BITMAP, h)},
+ {"BMP_CLIP", (uintptr_t)offsetof(BITMAP, clip)},
+ {"BMP_CL", (uintptr_t)offsetof(BITMAP, cl)},
+ {"BMP_CR", (uintptr_t)offsetof(BITMAP, cr)},
+ {"BMP_CT", (uintptr_t)offsetof(BITMAP, ct)},
+ {"BMP_CB", (uintptr_t)offsetof(BITMAP, cb)},
+ {"BMP_VTABLE", (uintptr_t)offsetof(BITMAP, vtable)},
+ {"BMP_WBANK", (uintptr_t)offsetof(BITMAP, write_bank)},
+ {"BMP_RBANK", (uintptr_t)offsetof(BITMAP, read_bank)},
+ {"BMP_DAT", (uintptr_t)offsetof(BITMAP, dat)},
+ {"BMP_ID", (uintptr_t)offsetof(BITMAP, id)},
+ {"BMP_EXTRA", (uintptr_t)offsetof(BITMAP, extra)},
+ {"BMP_XOFFSET",(uintptr_t)offsetof(BITMAP, x_ofs)},
+ {"BMP_YOFFSET",(uintptr_t)offsetof(BITMAP, y_ofs)},
+ {"BMP_SEG", (uintptr_t)offsetof(BITMAP, seg)},
+ {"BMP_LINE", (uintptr_t)offsetof(BITMAP, line)},
{"NEWLINE", 0},
{"#ifndef BMP_ID_VIDEO", 0}, // next lot are 0x%08X in original
{"BMP_ID_VIDEO", BMP_ID_VIDEO},
@@ -117,24 +117,24 @@
{"BMP_ID_MASK", BMP_ID_MASK},
{"#endif", 0 },
{"NEWLINE", 0},
-#ifndef ALLEGRO_USE_C
- {"CMP_PLANAR", (int)offsetof(COMPILED_SPRITE, planar)},
- {"CMP_COLOR_DEPTH", (int)offsetof(COMPILED_SPRITE, color_depth)},
- {"CMP_DRAW", (int)offsetof(COMPILED_SPRITE, proc)},
- {"NEWLINE", 0},
-#endif
- {"VTABLE_COLOR_DEPTH", (int)offsetof(GFX_VTABLE, color_depth)},
- {"VTABLE_MASK_COLOR", (int)offsetof(GFX_VTABLE, mask_color)},
- {"VTABLE_UNBANK", (int)offsetof(GFX_VTABLE, unwrite_bank)},
- {"NEWLINE", 0},
- {"RLE_W", (int)offsetof(RLE_SPRITE, w)},
- {"RLE_H", (int)offsetof(RLE_SPRITE, h)},
- {"RLE_DAT", (int)offsetof(RLE_SPRITE, dat)},
- {"NEWLINE", 0},
- {"GFXRECT_WIDTH", (int)offsetof(GRAPHICS_RECT, width)},
- {"GFXRECT_HEIGHT", (int)offsetof(GRAPHICS_RECT, height)},
- {"GFXRECT_PITCH", (int)offsetof(GRAPHICS_RECT, pitch)},
- {"GFXRECT_DATA", (int)offsetof(GRAPHICS_RECT, data)},
+#if !defined ALLEGRO_USE_C && defined ALLEGRO_I386
+ {"CMP_PLANAR", (uintptr_t)offsetof(COMPILED_SPRITE, planar)},
+ {"CMP_COLOR_DEPTH", (uintptr_t)offsetof(COMPILED_SPRITE, color_depth)},
+ {"CMP_DRAW", (uintptr_t)offsetof(COMPILED_SPRITE, proc)},
+ {"NEWLINE", 0},
+#endif
+ {"VTABLE_COLOR_DEPTH", (uintptr_t)offsetof(GFX_VTABLE, color_depth)},
+ {"VTABLE_MASK_COLOR", (uintptr_t)offsetof(GFX_VTABLE, mask_color)},
+ {"VTABLE_UNBANK", (uintptr_t)offsetof(GFX_VTABLE, unwrite_bank)},
+ {"NEWLINE", 0},
+ {"RLE_W", (uintptr_t)offsetof(RLE_SPRITE, w)},
+ {"RLE_H", (uintptr_t)offsetof(RLE_SPRITE, h)},
+ {"RLE_DAT", (uintptr_t)offsetof(RLE_SPRITE, dat)},
+ {"NEWLINE", 0},
+ {"GFXRECT_WIDTH", (uintptr_t)offsetof(GRAPHICS_RECT, width)},
+ {"GFXRECT_HEIGHT", (uintptr_t)offsetof(GRAPHICS_RECT, height)},
+ {"GFXRECT_PITCH", (uintptr_t)offsetof(GRAPHICS_RECT, pitch)},
+ {"GFXRECT_DATA", (uintptr_t)offsetof(GRAPHICS_RECT, data)},
{"NEWLINE", 0 },
{"DRAW_SOLID", DRAW_MODE_SOLID},
{"DRAW_XOR", DRAW_MODE_XOR},
@@ -151,61 +151,61 @@
{"MASK_COLOR_32", MASK_COLOR_32},
{"#endif", 0},
{"NEWLINE", 0},
- {"POLYSEG_U", (int)offsetof(POLYGON_SEGMENT, u)},
- {"POLYSEG_V", (int)offsetof(POLYGON_SEGMENT, v)},
- {"POLYSEG_DU", (int)offsetof(POLYGON_SEGMENT, du)},
- {"POLYSEG_DV", (int)offsetof(POLYGON_SEGMENT, dv)},
- {"POLYSEG_C", (int)offsetof(POLYGON_SEGMENT, c)},
- {"POLYSEG_DC", (int)offsetof(POLYGON_SEGMENT, dc)},
- {"POLYSEG_R", (int)offsetof(POLYGON_SEGMENT, r)},
- {"POLYSEG_G", (int)offsetof(POLYGON_SEGMENT, g)},
- {"POLYSEG_B", (int)offsetof(POLYGON_SEGMENT, b)},
- {"POLYSEG_DR", (int)offsetof(POLYGON_SEGMENT, dr)},
- {"POLYSEG_DG", (int)offsetof(POLYGON_SEGMENT, dg)},
- {"POLYSEG_DB", (int)offsetof(POLYGON_SEGMENT, db)},
- {"POLYSEG_Z", (int)offsetof(POLYGON_SEGMENT, z)},
- {"POLYSEG_DZ", (int)offsetof(POLYGON_SEGMENT, dz)},
- {"POLYSEG_FU", (int)offsetof(POLYGON_SEGMENT, fu)},
- {"POLYSEG_FV", (int)offsetof(POLYGON_SEGMENT, fv)},
- {"POLYSEG_DFU", (int)offsetof(POLYGON_SEGMENT, dfu)},
- {"POLYSEG_DFV", (int)offsetof(POLYGON_SEGMENT, dfv)},
- {"POLYSEG_TEXTURE", (int)offsetof(POLYGON_SEGMENT, texture)},
- {"POLYSEG_UMASK", (int)offsetof(POLYGON_SEGMENT, umask)},
- {"POLYSEG_VMASK", (int)offsetof(POLYGON_SEGMENT, vmask)},
- {"POLYSEG_VSHIFT", (int)offsetof(POLYGON_SEGMENT, vshift)},
- {"POLYSEG_SEG ", (int)offsetof(POLYGON_SEGMENT, seg)},
- {"POLYSEG_ZBADDR", (int)offsetof(POLYGON_SEGMENT, zbuf_addr)},
- {"POLYSEG_RADDR", (int)offsetof(POLYGON_SEGMENT, read_addr)},
+ {"POLYSEG_U", (uintptr_t)offsetof(POLYGON_SEGMENT, u)},
+ {"POLYSEG_V", (uintptr_t)offsetof(POLYGON_SEGMENT, v)},
+ {"POLYSEG_DU", (uintptr_t)offsetof(POLYGON_SEGMENT, du)},
+ {"POLYSEG_DV", (uintptr_t)offsetof(POLYGON_SEGMENT, dv)},
+ {"POLYSEG_C", (uintptr_t)offsetof(POLYGON_SEGMENT, c)},
+ {"POLYSEG_DC", (uintptr_t)offsetof(POLYGON_SEGMENT, dc)},
+ {"POLYSEG_R", (uintptr_t)offsetof(POLYGON_SEGMENT, r)},
+ {"POLYSEG_G", (uintptr_t)offsetof(POLYGON_SEGMENT, g)},
+ {"POLYSEG_B", (uintptr_t)offsetof(POLYGON_SEGMENT, b)},
+ {"POLYSEG_DR", (uintptr_t)offsetof(POLYGON_SEGMENT, dr)},
+ {"POLYSEG_DG", (uintptr_t)offsetof(POLYGON_SEGMENT, dg)},
+ {"POLYSEG_DB", (uintptr_t)offsetof(POLYGON_SEGMENT, db)},
+ {"POLYSEG_Z", (uintptr_t)offsetof(POLYGON_SEGMENT, z)},
+ {"POLYSEG_DZ", (uintptr_t)offsetof(POLYGON_SEGMENT, dz)},
+ {"POLYSEG_FU", (uintptr_t)offsetof(POLYGON_SEGMENT, fu)},
+ {"POLYSEG_FV", (uintptr_t)offsetof(POLYGON_SEGMENT, fv)},
+ {"POLYSEG_DFU", (uintptr_t)offsetof(POLYGON_SEGMENT, dfu)},
+ {"POLYSEG_DFV", (uintptr_t)offsetof(POLYGON_SEGMENT, dfv)},
+ {"POLYSEG_TEXTURE", (uintptr_t)offsetof(POLYGON_SEGMENT, texture)},
+ {"POLYSEG_UMASK", (uintptr_t)offsetof(POLYGON_SEGMENT, umask)},
+ {"POLYSEG_VMASK", (uintptr_t)offsetof(POLYGON_SEGMENT, vmask)},
+ {"POLYSEG_VSHIFT", (uintptr_t)offsetof(POLYGON_SEGMENT, vshift)},
+ {"POLYSEG_SEG ", (uintptr_t)offsetof(POLYGON_SEGMENT, seg)},
+ {"POLYSEG_ZBADDR", (uintptr_t)offsetof(POLYGON_SEGMENT, zbuf_addr)},
+ {"POLYSEG_RADDR", (uintptr_t)offsetof(POLYGON_SEGMENT, read_addr)},
{"NEWLINE", 0},
{"ERANGE", ERANGE},
{"NEWLINE", 0},
- {"M_V00", (int)offsetof(MATRIX_f, v[0][0])},
- {"M_V01", (int)offsetof(MATRIX_f, v[0][1])},
- {"M_V02", (int)offsetof(MATRIX_f, v[0][2])},
- {"M_V10", (int)offsetof(MATRIX_f, v[1][0])},
- {"M_V11", (int)offsetof(MATRIX_f, v[1][1])},
- {"M_V12", (int)offsetof(MATRIX_f, v[1][2])},
- {"M_V20", (int)offsetof(MATRIX_f, v[2][0])},
- {"M_V21", (int)offsetof(MATRIX_f, v[2][1])},
- {"M_V22", (int)offsetof(MATRIX_f, v[2][2])},
- {"NEWLINE", 0},
- {"M_T0", (int)offsetof(MATRIX_f, t[0])},
- {"M_T1", (int)offsetof(MATRIX_f, t[1])},
- {"M_T2", (int)offsetof(MATRIX_f, t[2])},
+ {"M_V00", (uintptr_t)offsetof(MATRIX_f, v[0][0])},
+ {"M_V01", (uintptr_t)offsetof(MATRIX_f, v[0][1])},
+ {"M_V02", (uintptr_t)offsetof(MATRIX_f, v[0][2])},
+ {"M_V10", (uintptr_t)offsetof(MATRIX_f, v[1][0])},
+ {"M_V11", (uintptr_t)offsetof(MATRIX_f, v[1][1])},
+ {"M_V12", (uintptr_t)offsetof(MATRIX_f, v[1][2])},
+ {"M_V20", (uintptr_t)offsetof(MATRIX_f, v[2][0])},
+ {"M_V21", (uintptr_t)offsetof(MATRIX_f, v[2][1])},
+ {"M_V22", (uintptr_t)offsetof(MATRIX_f, v[2][2])},
+ {"NEWLINE", 0},
+ {"M_T0", (uintptr_t)offsetof(MATRIX_f, t[0])},
+ {"M_T1", (uintptr_t)offsetof(MATRIX_f, t[1])},
+ {"M_T2", (uintptr_t)offsetof(MATRIX_f, t[2])},
{"NEWLINE", 0},
#ifdef ALLEGRO_DOS
- {"IRQ_SIZE", (int)sizeof(_IRQ_HANDLER)},
- {"IRQ_HANDLER", (int)offsetof(_IRQ_HANDLER, handler)},
- {"IRQ_NUMBER", (int)offsetof(_IRQ_HANDLER, number)},
- {"IRQ_OLDVEC", (int)offsetof(_IRQ_HANDLER, old_vector)},
- {"NEWLINE", 0},
- {"DPMI_AX", (int)offsetof(__dpmi_regs, x.ax)},
- {"DPMI_BX", (int)offsetof(__dpmi_regs, x.bx)},
- {"DPMI_CX", (int)offsetof(__dpmi_regs, x.cx)},
- {"DPMI_DX", (int)offsetof(__dpmi_regs, x.dx)},
- {"DPMI_SP", (int)offsetof(__dpmi_regs, x.sp)},
- {"DPMI_SS", (int)offsetof(__dpmi_regs, x.ss)},
- {"DPMI_FLAGS", (int)offsetof(__dpmi_regs, x.flags)},
+ {"IRQ_SIZE", (uintptr_t)sizeof(_IRQ_HANDLER)},
+ {"IRQ_HANDLER", (uintptr_t)offsetof(_IRQ_HANDLER, handler)},
+ {"IRQ_NUMBER", (uintptr_t)offsetof(_IRQ_HANDLER, number)},
+ {"IRQ_OLDVEC", (uintptr_t)offsetof(_IRQ_HANDLER, old_vector)},
+ {"NEWLINE", 0},
+ {"DPMI_AX", (uintptr_t)offsetof(__dpmi_regs, x.ax)},
+ {"DPMI_BX", (uintptr_t)offsetof(__dpmi_regs, x.bx)},
+ {"DPMI_CX", (uintptr_t)offsetof(__dpmi_regs, x.cx)},
+ {"DPMI_DX", (uintptr_t)offsetof(__dpmi_regs, x.dx)},
+ {"DPMI_SP", (uintptr_t)offsetof(__dpmi_regs, x.sp)},
+ {"DPMI_SS", (uintptr_t)offsetof(__dpmi_regs, x.ss)},
+ {"DPMI_FLAGS", (uintptr_t)offsetof(__dpmi_regs, x.flags)},
{"NEWLINE", 0},
#endif
#ifdef ALLEGRO_ASM_USE_FS
Index: src/i386/icpu.c
===================================================================
RCS file: /cvsroot/alleg/allegro/src/i386/icpu.c,v
retrieving revision 1.7
diff -u -r1.7 icpu.c
--- src/i386/icpu.c 6 Jan 2005 12:10:32 -0000 1.7
+++ src/i386/icpu.c 7 Mar 2005 10:26:54 -0000
@@ -30,7 +30,7 @@
void _i_cx_w(int index, int value);
char _i_cx_r(int index);
int _i_is_cpuid_supported(void);
-void _i_get_cpuid_info(long cpuid_levels, long *reg);
+void _i_get_cpuid_info(uint32_t cpuid_levels, uint32_t *reg);
@@ -92,15 +92,15 @@
*/
void check_cpu()
{
- long cpuid_levels;
- long vendor_temp[4];
- long reg[4];
+ uint32_t cpuid_levels;
+ uint32_t vendor_temp[4];
+ uint32_t reg[4];
cpu_capabilities = 0;
if (_i_is_cpuid_supported()) {
cpu_capabilities |= CPU_ID;
- _i_get_cpuid_info(0, reg);
+ _i_get_cpuid_info(0x00000000, reg);
cpuid_levels = reg[0];
vendor_temp[0] = reg[1];
vendor_temp[1] = reg[3];
@@ -128,7 +128,7 @@
}
_i_get_cpuid_info(0x80000000, reg);
- if ((unsigned long)reg[0] > 0x80000000) {
+ if (reg[0] > 0x80000000) {
_i_get_cpuid_info(0x80000001, reg);
cpu_capabilities |= (reg[3] & 0x80000000 ? CPU_3DNOW : 0);
Index: src/i386/icpus.s
===================================================================
RCS file: /cvsroot/alleg/allegro/src/i386/icpus.s,v
retrieving revision 1.1.1.1
diff -u -r1.1.1.1 icpus.s
--- src/i386/icpus.s 14 May 2000 20:17:13 -0000 1.1.1.1
+++ src/i386/icpus.s 7 Mar 2005 10:26:54 -0000
@@ -186,7 +186,7 @@
-/* void _i_get_cpuid_info(long cpuid_levels, long *reg);
+/* void _i_get_cpuid_info(uint32_t cpuid_levels, uint32_t *reg);
* This is so easy!
*/
FUNC(_i_get_cpuid_info)
Index: tests/test.c
===================================================================
RCS file: /cvsroot/alleg/allegro/tests/test.c,v
retrieving revision 1.32
diff -u -r1.32 test.c
--- tests/test.c 24 Oct 2004 11:49:10 -0000 1.32
+++ tests/test.c 7 Mar 2005 10:26:56 -0000
@@ -4442,9 +4442,13 @@
buttons = install_mouse();
sprintf(mouse_specs, "Mouse has %d buttons", buttons);
- #ifdef ALLEGRO_I386
+ #if defined ALLEGRO_I386 || defined ALLEGRO_AMD64
- sprintf(cpu_specs, "CPU family: %d86", cpu_family);
+ #ifdef ALLEGRO_I386
+ sprintf(cpu_specs, "CPU family: %d86", cpu_family);
+ #else
+ sprintf(cpu_specs, "CPU family: AMD64");
+ #endif
if (cpu_capabilities & CPU_ID)
strcat(cpu_specs, " / cpuid");
@@ -4461,6 +4465,9 @@
if (cpu_capabilities & CPU_SSE2)
strcat(cpu_specs, " / SSE2");
+ if (cpu_capabilities & CPU_SSE3)
+ strcat(cpu_specs, " / SSE3");
+
if (cpu_capabilities & CPU_MMX)
strcat(cpu_specs, " / MMX");
Attachment:
srcamd64.tar.gz
Description: application/tgz
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