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- To: chrony-users@xxxxxxxxxxxxxxxxxxxx
- Subject: Re: [chrony-users] Specifying refclock accuracy
- From: James Clark <jjc@xxxxxxxxxx>
- Date: Thu, 21 Sep 2023 10:07:00 +0700
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On Wed, Sep 20, 2023 at 4:40 PM Miroslav Lichvar <mlichvar@xxxxxxxxxx> wrote:
>
> On Wed, Sep 20, 2023 at 01:53:54PM +0700, James Clark wrote:
> > but the margin of error remains in the 700ns-800ns range. The margin
> > of error figure is similar to the dispersion figure in the refclocks
> > log, so I'm guessing that's the main cause. Why is the dispersion so
> > large and is there anything that can be done to fix it?
>
> It contains half of the delay in reading of the PHC, mostly coming
> from the PCIe delay. The only way to avoid that is cross timestamping
> (e.g. PTM).
I tried it with a PTM-enabled system (an i225-T1), and the margin of
error does indeed drop dramatically to 70ns.
The dispersion is 40ns. If I use the nocrossts option on that system,
the margin of error is about 1780ns and dispersion 1750ns.
I'm seeing occasional kernel messages (in version 6.1.52):
igc 0000:05:00.0 enp5s0: Timeout reading IGC_PTM_STAT register
Is that something I should report upstream somewhere?
Thanks for the other info: things are clearer now.
James
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