Re: Aw: Re: [hatari-devel] ST Doom crash with 16Mhz+cache MegaSTE

[Nicolas Pomarède <npomarede@xxxxxxxxxxxx>]

Le 11/06/2025 à 10:21, Nicolas Pomarède a écrit :
> Le 11/06/2025 à 10:17, Christian Zietz a écrit :
> > *It is bits 14-23 *(spread over two tag RAMs).
> > Please use the full tag to match the real Mega STE. Your patch below 
> > will just cause new, different crashes.
>
> you're right, this is what happens when trying to answer Atari's related 
> stuffs while working on other things at the same time :)
>
> I will come back to this later tonight wih a proper patch :)

Hi

Eero or Christian, see attached patch that uses 10 bits for the Tag 
instead of 8.

Can you check if ST Doom doesn't crash anymore ?

Note that you can also define MEGA_STE_CACHE_DEBUG_CHECK_ENTRIES to add 
on-the-fly consistency check of the cache

PS : I didn't test it myself, no MegaSTE program with me at the moment, 
but it should work :)

Nicolas

diff --git a/src/m68000.c b/src/m68000.c
index af19c42d..6b8e9f1d 100644
--- a/src/m68000.c
+++ b/src/m68000.c
@@ -156,14 +156,14 @@ const char *OpcodeName[] = { "ILLG",
 
 struct {
 	uint8_t		Valid[ MEGA_STE_CACHE_SIZE ];
-	uint8_t		Tag[ MEGA_STE_CACHE_SIZE ];
+	uint16_t	Tag[ MEGA_STE_CACHE_SIZE ];
 	uint16_t	Value[ MEGA_STE_CACHE_SIZE ];
 } MegaSTE_Cache;
 
 
 bool	MegaSTE_Cache_Is_Enabled ( void );
 bool	MegaSTE_Cache_Addr_Cacheable ( uint32_t addr );
-void	MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint8_t *pTag );
+void	MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint16_t *pTag );
 bool	MegaSTE_Cache_Update ( uint32_t Addr , int Size , uint16_t Val );
 bool	MegaSTE_Cache_Write ( uint32_t Addr , int Size , uint16_t Val );
 bool	MegaSTE_Cache_Read ( uint32_t Addr , int Size , uint16_t *pVal );
@@ -1068,7 +1068,7 @@ void M68000_MMU_Info(FILE *fp, uint32_t flags)
 /* The cache is made of 8192 lines, each line is 1 word (2 bytes)		*/
 /* When a physical address is accessed, the following bits are used to select	*/
 /* an entry in the TAG RAM :							*/
-/*  - bits 15-22 : tag (8 bits)							*/
+/*  - bits 15-24 : tag (10 bits)						*/
 /*  - bits 1-14 : line (0 to 8191)						*/
 /*  - bit 0 : ignored (because the cache stores 16 bit words)			*/
 /*										*/
@@ -1213,7 +1213,7 @@ void	MegaSTE_Cache_Check_Entries ( const char *txt );
 void	MegaSTE_Cache_Check_Entries ( const char *txt )
 {
 	uint16_t	Line;
-	uint8_t	Tag;
+	uint16_t	Tag;
 	uint32_t	Addr;
 
 	for ( Line=0 ; Line < MEGA_STE_CACHE_SIZE ; Line++ )
@@ -1253,11 +1253,11 @@ bool	MegaSTE_Cache_Addr_Cacheable ( uint32_t addr )
 	if ( ( addr < STRamEnd ) && ( addr < 0x400000 ) )
 		return true;
 
-#ifndef MEGA_STE_CACHE_DEBUG_CHECK_ENTRIES
+//#ifndef MEGA_STE_CACHE_DEBUG_CHECK_ENTRIES
 	/* TOS in ROM region can be cached */
 	if ( ( addr >= 0xE00000 ) && ( addr < 0xF00000 ) )
 		return true;
-#endif
+//#endif
 
 	/* Other regions can't be cached */
 	return false;
@@ -1288,16 +1288,16 @@ void	MegaSTE_Cache_Flush ( void )
 
 /*
  * Convert a cacheable address into a Line number in the cache and a Tag value
- * Addr lowest 22 bits are split into :
- *   - bits 14-21 : tag (8 bits)
+ * Addr lowest 24 bits are split into :
+ *   - bits 14-23 : tag (10 bits)
  *   - bits 1-13 : line (0 to 8191)
  *   - bit 0 : ignored (because the cache stores 16 bit words)
  */
 
-void	MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint8_t *pTag )
+void	MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint16_t *pTag )
 {
 	*pLineNbr = ( Addr >> 1 ) & 0x1fff;
-	*pTag = ( Addr >> 14 ) & 0xff;
+	*pTag = ( Addr >> 14 ) & 0x3ff;
 }
 
 
@@ -1321,7 +1321,7 @@ void	MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint8_t *
 bool	MegaSTE_Cache_Update ( uint32_t Addr , int Size , uint16_t Val )
 {
 	uint16_t	Line;
-	uint8_t		Tag;
+	uint16_t	Tag;
 
 	if ( !MegaSTE_Cache_Addr_Cacheable ( Addr ) )
 		return false;					/* data not cacheable */
@@ -1368,7 +1368,7 @@ bool	MegaSTE_Cache_Write ( uint32_t Addr , int Size , uint16_t Val )
 bool	MegaSTE_Cache_Read ( uint32_t Addr , int Size , uint16_t *pVal )
 {
 	uint16_t	Line;
-	uint8_t		Tag;
+	uint16_t	Tag;
 
 	if ( !MegaSTE_Cache_Addr_Cacheable ( Addr ) )
 		return false;					/* cache miss, data not cacheable */