Aw: Re: [hatari-devel] ST Doom crash with 16Mhz+cache MegaSTE

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It is bits 14-23 (spread over two tag RAMs).
 
 
Please use the full tag to match the real Mega STE. Your patch below will just cause new, different crashes.
 
Regards
Christian
Gesendet: Mittwoch, 11. Juni 2025 um 10:12
Von: "Nicolas Pomarède" <npomarede@xxxxxxxxxxxx>
An: hatari-devel@xxxxxxxxxxxxxxxxxxx, "Christian Zietz" <czietz@xxxxxxx>
Betreff: Re: [hatari-devel] ST Doom crash with 16Mhz+cache MegaSTE
Le 11/06/2025 à 08:20, Christian Zietz a écrit :
Eero Tamminen schrieb:

NOTE: Everything works fine at 16Mhz, crashes start only after MegaSTE
(16KB) cache is also enabled (from GENERAL.CPX).

Could this be additional Hatari cache handling issue?

I cannot say I fully understood Hatari's MSTE cache handling at first glance. But I wonder why it only uses bits 14-21 as tag:
https://github.com/hatari/hatari/blob/854422f30297be12f68b4e76e4f23c6f2beca4a6/src/m68000.c#L1290
... whereas the real MegaSTE uses bits 14-23:
https://docs.dev-docs.org/htm/search.php?find=Atari+Mega+STE+Schematic

Wouldn't a too short tag cause wrong cache hits when ST-RAM and ROM are cached?

Hi

indeed it seems that when I used the MegaSTE schematic I read it too quickly (and quality is rather blurry) and I didn't use the correct bit set for the tag value.

but it's no bits 14-23, because it gives 10 bits and tag value inside the MK48S74N-25 is 8 bits, not 10.

So from the schematic, not all bits are used continuously from the 24 bit address line, bits 14 and 15 are not used and tag is using bits 16-23 (8 bits), not 14-21.

Eero, can you try this change and see if the crash is gone :

~line 1297 :

void    MegaSTE_Cache_Addr_Convert ( uint32_t Addr , uint16_t *pLineNbr , uint8_t *pTag )
{
    *pLineNbr = ( Addr >> 1 ) & 0x1fff;
-    *pTag = ( Addr >> 14 ) & 0xff;
+    *pTag = ( Addr >> 16 ) & 0xff;
}

Note that MegaSTE_Cache_Check_Entries() will be wrong in that case, so you should disable MEGA_STE_CACHE_DEBUG_CHECK_ENTRIES
 for the moment.

 
 
 
 

 

 

 



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