Re: [hatari-devel] SCSI DMA Control |
[ Thread Index |
Date Index
| More lists.tuxfamily.org/hatari-devel Archives
]
- To: hatari-devel@xxxxxxxxxxxxxxxxxxx
- Subject: Re: [hatari-devel] SCSI DMA Control
- From: Uwe Seimet <Uwe.Seimet@xxxxxxxxx>
- Date: Thu, 3 Feb 2022 23:48:20 +0100
- Authentication-results: strato.com; dkim=none
- Dkim-signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1643928500; s=strato-dkim-0002; d=seimet.de; h=In-Reply-To:References:Message-ID:Subject:To:From:Date:Cc:Date:From: Subject:Sender; bh=kgclo3wQDIonkJ+iDLG9CUWKLvuXhvJQDNNbkcsusiU=; b=C4n26Xj0ufr1/hsOq1aYgcydLx1sMFs6NMIUL1R9ZL1JtkuDpmiCiu4dWWJ2l38fOa rZP0hobFrvGVcgmxD8K7p95ZqSqc76nbE2vQ9XAC9+DPpfutWoiUJn6C33hyb0m47F/u P2MFjnOPFJh9ZxQ7v1aWb6OiSmDolGgnnzRN1Hi5hPmNHdVy8QN611sgLy2nYUhgYRW+ PNlY2SqDHiMEPe0/oEUbZfBeTdKzQ2jlntesBITmdw6A0GThdPNnVjSKLczcny1X1cKz /lEBxlwS2FM07P6TTe67tXWbFw+NDVIxMuGlrYCWAi8/WYDJ6j6iD/7yKv3l1kW1lQNc PoaQ==
Hi Roger,
> I've found that looking at the Hatari code is often a useful way of
> understanding how real hardware works, although of course I realise that it may
> not always be 100% accurate.
>
> I have been trying to figure out why bit 7 of 0xff8715 on a real TT is set
> (that's part of SCSI DMA control). However, I couldn't find anywhere in Hatari
> that sets it. So I have 2 questions:
> (1) did I miss something?
> (2) even if Hatari never sets it, apparently real hardware does set it
> sometimes. Does anyone know the conditions that would set this bit? I looked
> in the TT030 Hardware Reference Manual, but all it said was that it is only set
> by reads, and it is cleared by a read.
I'm afraid I don't have more information on this bit except that it is
supposed to be set when there is a bus error during a DMA transfer. The
German Atari Profibuch, which is very detailed, also does not provide more
information. I doubt that Hatari fully implements the TT's SCSI chip, and in
particular not all possible error conditions.
If you have a scenario where this bit is set, wouldn't it be the best guess
to assume that exactly what the bit signals has actually happened? The
transfer address might simply not be valid. At least that's my understanding
of what this bit means.
Take care
Uwe