Re: [hatari-devel] FPU status register handling & fmovem.x bugs

[Toni Wilen <twilen@xxxxxxxxxx>]

>> 68040 FPCR is different: 000000FFFF (4 undefined bits are read/write).
> 
> That's really strange. The 68040UM has the same info as the 68000PRM:

There is another similar difference between 68040 and 68060: MMU URP and
SRP registers are full 32-bit in 68040 but bits 0 to 8 always read as
zero in 68060. (Bits that must be zero when setting MMU table pointers).

Undefined bits are undefined.

There may be others, I did test them long time ago but I may have missed
some.