|Re: [hatari-devel] Suspicious instruction & data cache hit/miss accounting|
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Le 02/02/2018 à 00:18, Eero Tamminen a écrit :
Disassembly shows only i-cache misses and d-cache hits, so
from that you don't know whether something is missing.
but if you add your own printf after disasm to print all hit/miss
counters after each instructions ?
However, for i-cache, I think it's clear from the CPU core sources
that they're counted only for instructions that trigger either
prefetch or pipeline stall (=branch).
Do you agree on that interpretation? Because then:
* Those hit/miss counts also tell how often those events happens
* It should be fine to translate (on the profiler side) any
instruction that doesn't generate a miss, as being a hit.
What I don't understand for i-cache, is how you can get multiple
hits or misses for single instruction. Instructions are all
word sized & word aligned, so they cannot cross cache line
boundary, so there should be only zero or one hit / miss,
And what about data cache? I can understand 2 misses if
data is e.g. long crossing cache line, but what about larger
numbers? Or is it about how much data the miss caused to
be fetched to the cache?
A movem could generate several cache misses.
But it's hard to conclude anything without any real opcode example.
Maybe some are perfectly normal, maybe for some I forgot to count some
hit/miss, hard to tell without actual instructions leading to these results.