[hatari-devel] Suspicious instruction & data cache hit/miss accounting

[Eero Tamminen <oak@xxxxxxxxxxxxxx>]

Hi,

I was looking at this thing we had wondered before:
--------------------------------------
> profile caches

Instruction cache hits per instruction, number of occurrences:
  0: ############################################ 87.686%
  1: ###### 10.038%
  2: # 1.924%
  3: # 0.352%

Instruction cache misses per instruction, number of occurrences:
  0: ################### 37.134%
  1: ################## 35.387%
  2: ########### 21.447%
  3: #### 6.024%

Data cache hits per instruction, number of occurrences:
  0: ########################################### 84.227%
  1: ###### 10.528%
  2: ## 3.585%
  3: # 0.387%

Data cache misses per instruction, number of occurrences:
  0: ###################################### 74.093%
  1: ########### 20.772%
  2: ## 3.993%
  3: # 0.353%
--------------------------------------

I.e. how/why most of instructions have *neither* cache hits or misses?


Based on our WinUAE code, it seems that instruction cache hits & misses
aren't counted for pipelined instructions, only for instructions
requiring cache fill, either because there's a branch or prefetch.

While accounting can be fixed later e.g. to mark anything not causing
misses as having a hit, I wonder whether the miss stats are correct.
Any comments?

(And as you can see, some of the executed instructions can incur
multiple i-cache hits or misses.)


I'm not sure why same happens for data cache.  I think hits & misses
are skipped in the CPU emulation core only if data cache is disabled.

However, above case is EmuTOS idling in TOS desktop.  I don't think
it would be toggling data cache on & off...

Would it be possible that largest part of memory accesses are done
through accessors that actually don't go through data cache checks?


	- Eero