[hatari-devel] SCC register handling on TT

[Eero Tamminen <oak@xxxxxxxxxxxxxx>]

Hi,

When looking at SCC register handling in relation to:
http://www.atari-forum.com/viewtopic.php?f=51&t=29989&p=306208#p306208

Hatari isn't yet emulating SCC, but I started to wonder
about Hatari's handling of non-implemented SCC registers...

From what I see from ioMem*.c sources on SCC regs access:
* ST & STE bus error
  -> corresponds to bus error tester results
* Deliberately voided for Falcon STE compat mode (ioMem.c)
  -> corresponds to bus error tester results
* Deliberately voided for normal Falcon mode (ioMemTabFalcon.c)
  -> corresponds to bus error tester results
* Bus error for TT
  -> does NOT correspond to bus error tester results
	$FF8C20 - $FF8C80
	$FF8C90 - $FF8E01

Is above interpretation right?

Thomas, does above bus error test mean that $FF8C80
generates bus error or not (i.e. is the output range
inclusive or exclusive or range end)?


	- Eero