Re: [hatari-devel] DSP performance

[Toni Wilen <twilen@xxxxxxxxxx>]

> So, in instruction cache mode, NOP is 0 head, 0 tail and 2 cycles)
>
> But in non cached mode, there's one access to the bus, so the cycles
> taken by the instruction is 4 cycles, not 2 (I'll try to find again the
> rule behing this).
> That's why I recomputed the whole table by hand to have the Falcon 16
> bit bus values and not the 68030 default 32 bit bus ones

NOP is not a good generic cycle usage test case because it waits until 
all pending memory cycles are complete. Emulation ignores this (Because 
I forgot about it)

That probably explains extra 2 cycle time. (Assuming memory cycles are 
without wait-states = 2 cycles/access)