Re: [hatari-devel] DSP performance

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    4 cycles because it has 16bit bus and does 2 16-bit fetches? (2x2)
    or does it really take 2x4 cycles to fetch 32-bit word?

Yes, it's both :) Two 16-bit prefetches and each of them takes 4 cycles.

I still must be missing something..

If this is true, then there is no way for NOP to take 4 cycles to execute. Either it takes 2 cycles (cache or next opcode word already in prefetch buffer) or it takes at least 8 cycles.

Is NOP=4 cycles measured 100% accurately (using external test hardware) or using some loop where it is too easy to get bad results, for example if there is multiple NOPs back to back and only every other NOP needs to do memory fetch.

(I still haven't done any real 68020/030 logic analyzer tests, when I finally bother to do it and have all required hardware, I can measure 16-bit accesses 100% accurately)

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