Re: [hatari-devel] DSP bug: need more explanations

[Nicolas Pomarède <npomarede@xxxxxxxxxxxx>]

Le 04/01/2015 23:54, Laurent Sallafranque a écrit :
> Yes, it seems to make sense now, your explanation is cristal clear for
> me now ;)
> Just have to see how to implement this in the actual code ;)

Hi

do handle this, maybe you could have an internal clock counter 
associated to each register to know when it was last modified.

I don't know if there's already a global cycle counter in the DSP code ? 
A counter that would always increase :
  dsp_global_counter += dsp_core.instr_cycle

Each time the registers with the "pipeline" effect are modified, you 
store the value of dsp_global_counter and the new value in "new_value".
When one of this register needs to be read later, you can do thg like 
(pseudo code) to return either the old/current "value" or the new 
"new_value" :

assuming you create a struct for these special registers :

struct {
 value;
 new_value;
 last_write_counter
}

 if ( dsp_global_counter - reg.last_write_counter > reg.propagation_delay )
   reg.value = reg.new_value;
   return reg.value;
 else
   return reg.value

If all regs have the same delay to propagate, you can replace 
"reg.propagation_delay" by a constant from a #define.

Nicolas