|Re: [hatari-devel] DSP and HREQ|
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Le 28/01/2015 23:20, Laurent Sallafranque a écrit :
To stop the interrupt, one just have to write a zero at bit 0 or 1 of
the ICR ($ffffa200.w)
In hatari, there's a call to dsp_core_hostport_update_hreq() when one
write at the ICR address, which is correct.
The remaining question is : should the HREQ exception should be removed
in this case.
I'm now ready to test the full send or receive process with the value of
HREQ as asked ;)
To be noticed : my program doesn't crash anymore now that I have the
correct vector address value ;)
yes, I think the part that sets hreq is correct, but I think that when
we clear TX or RX bit, it should clear the hreq line and there should
not be an interrupt anymore pending on the cpu side.
That's how the "test 2" case should check it : by setting SR=2700 at
start, this prevents the hreq to be handled by the cpu, then we clear
hreq by writing in ICR, and then we set SR=2500.
If hreq was really cleared, then there should be no interrupt called at
$3fc when we allow the level 6 interrupt again.