Re: [hatari-devel] add support for TT ram ?

[Douglas Little <doug694@xxxxxxxxxxxxxx>]

Here is the reverse-engineered PMMU tree from TOS 4.04.

In fact on a second look it does appear to map more than 16MB already, so it should work! It actually repeats every 256mb, not every 16. Just the table entries have a grain of 16mb.

entries:

ET = early termination descriptor

TB = table

flags:

T = table

U = used (read)

M = modified (written)

S = short descriptor format

CI = cache-inhibited (hardware regs / ext device)

; CRP -> TA[0]

;

;$700 TA[0,0] ($00000000->$0fffffff) -> TB[0] ($0000074a) T/U/SHORT

; TA[0,1] ($10000000->$1fffffff) -> ET ($10000001) P

; TA[0,2] ($20000000->$2fffffff) -> ET ($20000001) P

; TA[0,3] ($30000000->$3fffffff) -> ET ($30000001) P

; TA[0,4] ($40000000->$4fffffff) -> ET ($40000001) P

; TA[0,5] ($50000000->$5fffffff) -> ET ($50000001) P

; TA[0,6] ($60000000->$6fffffff) -> ET ($60000001) P

; TA[0,7] ($70000000->$7fffffff) -> ET ($70000001) P

; TA[0,8] ($80000000->$8fffffff) -> ET ($80000041) P/CI

; TA[0,9] ($90000000->$9fffffff) -> ET ($90000041) P/CI

; TA[0,a] ($a0000000->$afffffff) -> ET ($a0000041) P/CI

; TA[0,b] ($b0000000->$bfffffff) -> ET ($b0000041) P/CI

; TA[0,c] ($c0000000->$cfffffff) -> ET ($c0000041) P/CI

; TA[0,d] ($d0000000->$dfffffff) -> ET ($d0000041) P/CI

; TA[0,e] ($e0000000->$efffffff) -> ET ($e0000041) P/CI

; TA[0,f] ($f0000000->$ffffffff) -> TB[1] ($0000078a) T/U/SHORT

;

;

;$740 TB[0,0] ($00000000->$00ffffff) -> TC[0] ($000007ca) T/U/SHORT

; TB[0,1] ($01000000->$01ffffff) -> ET ($01000001) P

; TB[0,2] ($02000000->$02ffffff) -> ET ($02000001) P

; TB[0,3] ($03000000->$03ffffff) -> ET ($03000001) P

; TB[0,4] ($04000000->$04ffffff) -> ET ($04000001) P

; TB[0,5] ($05000000->$05ffffff) -> ET ($05000001) P

; TB[0,6] ($06000000->$06ffffff) -> ET ($06000001) P

; TB[0,7] ($07000000->$07ffffff) -> ET ($07000001) P

; TB[0,8] ($08000000->$08ffffff) -> ET ($08000001) P

; TB[0,9] ($09000000->$09ffffff) -> ET ($09000001) P

; TB[0,a] ($0a000000->$0affffff) -> ET ($0a000001) P

; TB[0,b] ($0b000000->$0bffffff) -> ET ($0b000001) P

; TB[0,c] ($0c000000->$0cffffff) -> ET ($0c000001) P

; TB[0,d] ($0d000000->$0dffffff) -> ET ($0d000001) P

; TB[0,e] ($0e000000->$0effffff) -> ET ($0e000001) P

; TB[0,f] ($0f000000->$0fffffff) -> ET ($0f000001) P

;

;$780 TB[1,0] ($f0000000->$f0ffffff) -> ET ($f0000041) P/CI

; TB[1,1] ($f1000000->$f1ffffff) -> ET ($f1000041) P/CI

; TB[1,2] ($f2000000->$f2ffffff) -> ET ($f2000041) P/CI

; TB[1,3] ($f3000000->$f3ffffff) -> ET ($f3000041) P/CI

; TB[1,4] ($f4000000->$f4ffffff) -> ET ($f4000041) P/CI

; TB[1,5] ($f5000000->$f5ffffff) -> ET ($f5000041) P/CI

; TB[1,6] ($f6000000->$f6ffffff) -> ET ($f6000041) P/CI

; TB[1,7] ($f7000000->$f7ffffff) -> ET ($f7000041) P/CI

; TB[1,8] ($f8000000->$f8ffffff) -> ET ($f8000041) P/CI

; TB[1,9] ($f9000000->$f9ffffff) -> ET ($f9000041) P/CI

; TB[1,a] ($fa000000->$faffffff) -> ET ($fa000041) P/CI

; TB[1,b] ($fb000000->$fbffffff) -> ET ($fb000041) P/CI

; TB[1,c] ($fc000000->$fcffffff) -> ET ($fc000041) P/CI

; TB[1,d] ($fd000000->$fdffffff) -> ET ($fd000041) P/CI

; TB[1,e] ($fe000000->$feffffff) -> ET ($fe000041) P/CI

; TB[1,f] ($ff000000->$ffffffff) -> TC[0] ($000007ca) U/SHORT

;

;$7c0 TC[0,0] ($00000000->$000fffff) -> ETP ($00000019) M/U/P

; TC[0,1] ($00100000->$001fffff) -> ETP ($00100019) M/U/P

; TC[0,2] ($00200000->$002fffff) -> ETP ($00200019) M/U/P

; TC[0,3] ($00300000->$003fffff) -> ETP ($00300019) M/U/P (4mb ram)

; TC[0,4] ($00400000->$004fffff) -> ETP ($00400009) U/P

; TC[0,5] ($00500000->$005fffff) -> ETP ($00500009) U/P

; TC[0,6] ($00600000->$006fffff) -> ETP ($00600009) U/P

; TC[0,7] ($00700000->$007fffff) -> ETP ($00700009) U/P

; TC[0,8] ($00800000->$008fffff) -> ETP ($00800009) U/P

; TC[0,9] ($00900000->$009fffff) -> ETP ($00900009) U/P

; TC[0,a] ($00a00000->$00afffff) -> ETP ($00a00009) U/P

; TC[0,b] ($00b00000->$00bfffff) -> ETP ($00b00009) U/P

; TC[0,c] ($00c00000->$00cfffff) -> ETP ($00c00009) U/P

; TC[0,d] ($00d00000->$00dfffff) -> ETP ($00d00019) M/U/P (14mb display ram?)

; TC[0,e] ($00e00000->$00efffff) -> ETP ($00e00009) U/P

; TC[0,f] ($00f00000->$00ffffff) -> ETP ($00f00059) M/U/P/CI (HW regs)

; TT0: 0xxx.xxx1:0111.1110:1000.00x1:0xxx.0111

; $01000000-$01xxxxxx / TT ram?

; enabled, FC ignored, RW ignored

;

; TT1: 1xxx.xxx0:0111.1110:1000.01x1:0xxx.0111

; $FE000000-$FExxxxxx / VME? 

; enabled, FC ignored, RW ignored

;

; TC: 1000.0000:1111.0000:0100.0100:0100..0101

; enabled, SRE disabled, FCL disabled, PS=32k, IS=0, TIA=4bits, TIB=4bits, TIC=4bits, TID=5bits(unused)

;

; CRP: 1000.0000:0000.0000:0000.0000:0000.0010

; 0000.0000:0000.0000:0000.0111:0000.0000

; lowerlimit/limit==0: limiting off, short(4byte) descriptors

; tree root = $700

;

; SRP: xxxx.xxxx:xxxx.xxxx:xxxx.xxxx:xxxx.xxxx ...random nonsense!

; xxxx.xxxx:xxxx.xxxx:xxxx.xxxx:xxxx.xxxx

On 11 December 2014 at 10:51, Nicolas Pomarède <npomarede@xxxxxxxxxxxx> wrote:

Le 11/12/2014 11:22, Thomas Reiss a écrit :

The CT60 has its owned patched TOS 4.04. The binary patch is available
on Didier Mequignon's homepage and the source code is available on
Anders's website : http://files.dhs.nu/files_util/ct60_404_all.zip

Hi

thanks for the link, I didn't know it.

The sdram detection part there is rather similar to the one in the TT TOS.

On a side note : part of these files look *really* similar to a direct disassembly of the original TOS, not that it really matters nowadays, but I think Atari could have been able to sue them for reusing copyrighted TOS code in their patched TOS version :)

Nicolas