Re: [AD] Allegro 4.2.0 RC1 timetable |
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On Sunday 05 June 2005 03:58, Peter Wang wrote:
> Yes, as per http://www.allegro.cc/forums/view_thread.php?_id=494345
> in case some here didn't see it:
>
> IA32/asm: fixmulasm, fixdivasm
> IA32/C: fixmuli, fixdivf
> otherwise: fixmull, fixdivf
>
> You can change fixdivf to fixdivl for non-IA32 platforms if you figure
> out the problem.
Hmm... unfortunately, for AMD64 at least it doesn't seem so simple. Using
the same optimisation switches Allegro uses, the assembler output for
inline fixed fixdivl(fixed x, fixed y)
{
if (y == 0) {
return (x < 0) ? -0x7FFFFFFF : 0x7FFFFFFF;
}
else {
long long lx = x;
long long ly = y;
long long lres = (lx << 16) / ly;
int res = lres;
return res;
}
}
looks like this
fixdivl:
.LFB21:
testl %esi, %esi
jne .L40
movl %edi, %eax
sarl $31, %eax
andl $2, %eax
addl $2147483647, %eax
ret
.p2align 4,,7
.L40:
movslq %edi,%rax
movslq %esi,%rdx
salq $16, %rax
movq %rdx, %rcx
cqto
idivq %rcx
ret
which to me doesn't look like it could be more optimal. In other words, I
think 64 bit division on the AMD64 is just dog slow.
Evert