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- To: chrony-users@xxxxxxxxxxxxxxxxxxxx
- Subject: Re: [chrony-users] Accurately measuring clock drift
- From: Miroslav Lichvar <mlichvar@xxxxxxxxxx>
- Date: Wed, 21 Jun 2023 12:41:09 +0200
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On Tue, Jun 20, 2023 at 12:35:25PM -0700, Thangalin wrote:
> It's armv7l running kernel 4.14 with chrony 3.4.
If it's using a GPIO pin, you can try this polling variant of the
pps-gpio driver to avoid interrupt delays:
https://github.com/mlichvar/pps-gpio-poll
When the module loads, it logs the delay in reading of the GPIO pin,
so you have an upper bound on the error.
> How would you go about measuring the clock drift between NTP and chrony so
> as to verify the drift has been reduced?
You need to use one source of information in both tests. With
a PPS device you can log the raw PPS offset reported in
/sys/class/pps/pps0/assert.
--
Miroslav Lichvar
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