[chrony-users] Inaccurate jiffy calculation at boot (x86 & 2.6.37)

[Ed W <lists@xxxxxxxxxxxxxx>]

My device will be only intermittently connected to an internet source,
so I'm trying to keep my clock as accurate as I can during disconnected
periods

At present I'm seeing my RTC is staying moderately consistent (give or
take it's computed loss rate).  However, when I reboot my device (Alix
2c from PCEngines) I see the calculated jiffies value vary by up to a
hundred or so ppm each time, eg:

[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 498.096 MHz processor.
[    0.001010] Calibrating delay loop (skipped), value calculated using
timer frequency.. 996.19 BogoMIPS (lpj=498096)

[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 498.081 MHz processor.
[    0.002010] Calibrating delay loop (skipped), value calculated using
timer frequency.. 996.16 BogoMIPS (lpj=498081)

[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 498.122 MHz processor.
[    0.003010] Calibrating delay loop (skipped), value calculated using
timer frequency.. 996.24 BogoMIPS (lpj=498122)

[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 498.065 MHz processor.
[    0.003010] Calibrating delay loop (skipped), value calculated using
timer frequency.. 996.13 BogoMIPS (lpj=498065)


As near as I can tell this causes Chrony to re-read it's stored tracking
values which are then quite inaccurate and cause the clock to drift
quite rapidly?  Each time I reboot chrony needs a network connection to
figure out the actual clock freq?

Any suggestions on how to get my clock more accurate (kernel 2.6.37 /
chrony git)?
- Can I patch init/calibrate.c to get it to figure out a better lpj
estimate?
- Can I have chrony use my RTC as a source? My RTC is much more accurate
at boot than the cpu clock? This seems to be possible with ntpd?
- Could chrony save some knowledge of the last lpj figure and use that
to update it's knowledge of my frequency offset (ie assume that the lpj
is in fact a constant, but avoid hard coding this onto the kernel boot
line?)



....Part of my problem is that the Alix board has an odd high speed clock
running at some multiple of 1024Hz. I think it should be possible to set
my kernel to HZ=1024 instead of HZ-1000, but I can't quite see how to
patch that yet? (Hints appreciated?)

Thanks for any pointers on this?

Ed W

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