Thank you very much, I will try again with this bitfile and tell you
how it goes.
Hi Denis.
That is
actually
normal - you need this FPGA bitfile, which implements the proper
timer
interrupt (otherwise the scheduler never runs):
If you build
an
FPGA-enabled design - see 2nd video - and perform a synthesis,
you'll get
a bitfile that actually works.
In pure-SW
designs
on the R5 alone, you need a bitfile that pulses the timer
interrupt - try
the attached one and tell me what you see.
With kindest
regards,
Thanassis.
Thanassis
Tsiodras
Real-time
Embedded
Software Engineer
System,
Software
and Technology Department
ESTEC
Keplerlaan 1,
PO Box 299
NL-2200 AG
Noordwijk,
The Netherlands
T +31 71 565
5332
Date:
28/03/2022
16:19
Subject:
[taste-users]
BRAVE Large under TASTE example problem
Hi, in our laboratory we would
be
interested in using freeRTOS on the
Brave NG-Large.
I'm trying to make the example shown on this video
https://www.youtube.com/watch?v=SDyT9QWP7Vo to work.
I can't manage to get the same result. When launching the code
with "c"
in gdb, only "[fun" is written on minicom (meaning the 4 first
characters) and the application hangs for ever.
When I do it step by step, the full first line get written in
minicom
but at some point the application ends at the line "undefined
handler"
of vector.S as shown below (log from gdb):
0x00006750 in pxCurrentTCB ()
Single stepping until exit from function pxCurrentTCB,
which has no line number information.
0x00006754 in pxReadyTasksLists ()
Single stepping until exit from function pxReadyTasksLists,
which has no line number information.
_vector_table () at
/home/taste/tmp_taste_aladede/Largefirsttryadede/work/build/node_1/partition_1/runtime/src/freertos/vector.S:40
40 b Undefined
Undefined () at
/home/taste/tmp_taste_aladede/Largefirsttryadede/work/build/node_1/partition_1/runtime/src/freertos/vector.S:57
57 Undefined: b .
@ Undefined handler
timeout waiting for target halt
Does someone know what could lead to this situation?
Secondly, the video doesn't say anything about the bitstream
loaded in
the FPGA. I tried to compile the example design given in the
repo
(TAST-VHDL-DESIGN.tar.bz2) but some files seem to be missing.
What FPGA
design should we use for this example?
Denis Perret
This message is intended only for the recipient(s) named above. It may contain proprietary information and/or
protected content. Any unauthorised disclosure, use, retention or dissemination is prohibited. If you have received
this e-mail in error, please notify the sender immediately. ESA applies appropriate organisational measures to protect
personal data, in case of data privacy queries, please contact the ESA Data Protection Officer (dpo@xxxxxxx).