Re: [hatari-devel] Dynamic Bus Sizing and I/O Register Access

Am 18.01.2024 um 17:37 schrieb Andreas Grabher <andreas_g86@xxxxxxxxxx>:

Am 17.01.2024 um 19:06 schrieb Toni Wilen <twilen@xxxxxxxxxx>:

>The chip is a custom designed chip for direct memory access. It has 32-bit long command/status registers. They contain readable status bits in 0x00XX0000 and >writeable command bits in 0xXX000000. The registers are always accessed at their base address 0x02000010 using byte access on early 68030-only software and >long access on later software that runs on both 68030 and 68040.
>
>Access on 68030 is for example using MOVE.B (An),Dn or BTST.B #<data>.W,(An) for read and using MOVE.B #<data>.B,(An) or CLR.B (An) for write.
>
>Correction: Readable status bits at 0xXX000000 and writeable command bits at 0x00XX0000.

More details, please. Same long write compared to byte write (and read) code needed. Also above byte wide examples misses the address, at least last 2 address bits are needed.

Long write is MOVE.L #<data>.B,(An). All access (read/write/byte/long) are to address 0x02000010 (A0 and A1 are 0).

Typo! It is of course MOVE.L #<data>.L,(An).

Is it possible status bits are returned in all 4 bytes? (even if officially you are supposed to use bits 24-31 and ignore others, it might have simplified the internal chip design). Are the all registers similar? Long wide but only return byte wide data?

Yes, this is possible. But I have no real hardware to test it. The chip also has 32-bit address pointer registers. These are always accessed with long wide instructions (even on old system) and contain addresses that occupy all 4 bytes.

From: Andreas Grabher <andreas_g86@xxxxxxxxxx>
Sent: 16 January 2024 21:06
To: hatari-devel@xxxxxxxxxxxxxxxxxxx <hatari-devel@xxxxxxxxxxxxxxxxxxx>
Subject: Re: [hatari-devel] Dynamic Bus Sizing and I/O Register Access

Am 16.01.2024 um 19:19 schrieb Andreas Grabher <andreas_g86@xxxxxxxxxx>:

Am 16.01.2024 um 08:57 schrieb Toni Wilen <twilen@xxxxxxxxxx>:

>Thank you Toni! Can you point me to the place in WinUAE where this is handled (if Amiga has any such case)?
>Maybe I am able to understand this by reading the code. The description in the data sheet is confusing me.

Don't have any examples now but the device seems to be designed to only have 32-bit wide registers and bits 0 and 1 of address bus are not connected (or most likely don't even exist to save pins). CPU sees it as 32-bit device, I don't think this case needs bus sizing needed (no need to split the access)

This is feels somewhat similar to Amiga and 53C710 (and later) SCSI chips that only have 32-bit registers but some drivers still use byte reads to check some status bits. Nothing special is needed, except endian-swapping. (which in case of reading bytes means address 3 becoming address 0, 2 becomes 1 and so on)

More details needed. (chip type, register that is read using both byte and long -wide instructions, exact instructions used)

The chip is a custom designed chip for direct memory access. It has 32-bit long command/status registers. They contain readable status bits in 0x00XX0000 and writeable command bits in 0xXX000000. The registers are always accessed at their base address 0x02000010 using byte access on early 68030-only software and long access on later software that runs on both 68030 and 68040.

Access on 68030 is for example using MOVE.B (An),Dn or BTST.B #<data>.W,(An) for read and using MOVE.B #<data>.B,(An) or CLR.B (An) for write.

Correction: Readable status bits at 0xXX000000 and writeable command bits at 0x00XX0000.