| Re: [hatari-devel] TT hardware memory information |
[ Thread Index |
Date Index
| More lists.tuxfamily.org/hatari-devel Archives
]
On 12 Mar 2016 at 7:37, Thomas Huth wrote:
> Am Fri, 11 Mar 2016 22:15:21 -0500
> schrieb "Roger Burrows" <anodyne@xxxxxxxxxxxx>:
>
> > Just posting some TT hardware info as it comes my way (as I try to
> > get EmuTOS to run on real TT hardware).
> >
> > ST-RAM memory support
> > ---------------------
> > There are 3 valid ST-RAM configurations:
> > 1. 2MB: this is socketed memory on the motherboard
> > 2. 4MB: this adds a 2MB daughter board above the socketed memory
> > 3. 10MB: this adds an 8MB daughter board above the socketed memory
> >
> > Memory controller values (i.e. what gets written to 0xff8001, and
> > stored in the byte at 0x424 by TOS/EmuTOS):
> > 1. 2MB: 0x05
> > 2. 4MB: 0x05
> > 3. 10MB: 0x0a
>
> Thanks for the info! ... of course that raises now the question whether
> this register does make any sense on the TT at all - if both 2 MB and 4
> MB take the same value?
>
I'm pretty sure it does; at least, TOS sets a default value, does a simple test
to determine whether addresses are unique, and then updates the value if the
test says they (currently) aren't. I can upload the relevant disassembly if
you want to look for yourself.
Roger