|[hatari-devel] 68020 logic analyzer testing|
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> (I still haven't done any real 68020/030 logic analyzer tests, when I
> finally bother to do it and have all required hardware, I can measure
> 16-bit accesses 100% accurately)
I finally have 68020 board that I can use to trace instruction prefetch
and memory access order 100% accurately and hopefully also some idle
cycle timings (*).
Do you have any suggestions for test cases?
I have already confirmed that most branching instruction really do stop
prefetches immediately after last needed instruction word has been
fetched. (Previously only "seems to be true" confirmed by playing with
instruction cache prefetch side-effects)
*) It is Individual Computers ACA1221 at about 9MHz connected ACA500
which is connected to Amiga 500 and my logic analyzer is connected to
A500's data bus (only because A500 is not surface mount!).
This means bus is 16-bit (32-bit would also have required too many logic
analyzer channels) which probably also means at least some idle cycles
will be unfortunately hidden by longer bus cycles (2x16 vs 1x32).