Re: [hatari-devel] 68030 instruction time calculation formulae

[Toni Wilen <twilen@xxxxxxxxxx>]

Hi

I finally decided to join this list, recent UAE CPU and CPU topics seem 
to be interesting enough, even if emulated platform is wrong :)

> The link below may be useful when looking at emulation timings vs real
> world (at least, for cached code - the uncached code case is more
> complex to match exactly, albeit perhaps less important to do so for emu
> purposes)

Unfortunately that information is not low level enough. It can't be used 
to re-create how CPU internal sequencer exactly works which is the only 
way to get real cycle-exact emulation. Cache case should be already 
quite accurate, minus instructions that need internal operation cycles 
like MUL and DIV and others.

Also one important missing part is prefetch logic timing, in other 
words, how does CPU choose when to prefetch instruction words and when 
to do data read/write operation. This seems to be main problem getting 
non-cache case accurate enough.

Timing examples in documentation are too short to be able to find any 
clues. It is Impossible to get good enough accuracy just by looking at 
documentation.

>  From what I could tell on discussions on EAB, some of these
> calculations are still being figured out and integrated into UAE (partly
> due to its basis in 68020 and having less info on that chip) so I don't

UAE m68k emulator already uses information from both 68020 and 68030 
documentation (head/tail/internal cycles). 68030 more or less seems to 
be 68020 with 1 cycle faster memory access + some small instruction 
timing changes.

> know how far they actually got with that effort using the 030 info.
> Perhaps it has already been 100% solved since - I don't know. In any
> case this book is probably the primary source to which we should be
> referring for accuracy :)

I will have real world test hardware available later, slow A1200 68EC020 
accelerator board connected to 16-bit Amiga (Using ACA500) that I can 
use to check memory access cycle order and timing with my logic 
analyzer. 16-bit because I don't have enough channels in logic analyzer 
for 32bit data + other important signals, of course timing won't be same 
as with 32-bit data bus but I am much more interested in memory access 
cycle order. (Especially instruction pipeline behavior vs data accesses)

I am still not sure when I am going to do it, it will be extremely boring..