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<div dir=3D"ltr"><div><div><div><br>The link below may be useful when looki=
ng at emulation timings vs real world (at least, for cached code - the unca=
ched code case is more complex to match exactly, albeit perhaps less import=
ant to do so for emu purposes)<br><br><a href=3D"http://cache.freescale.com=
/files/32bit/doc/ref_manual/MC68030UM-P2.pdf">http://cache.freescale.com/fi=
les/32bit/doc/ref_manual/MC68030UM-P2.pdf</a><br><br></div>See page #187 &q=
uot;Instruction Execution Timing Calculations" and in particular secti=
on 11.3.4 on EA adjustments and instruction overlaps, and the summing formu=
la provided.<br><br></div><div>[Caveat: the text assumes bus events consume=
2 cycles always, which is not true for us, add needs accounted for where i=
t matters]<br></div><div><br><br></div>From what I could tell on discussion=
s on EAB, some of these calculations are still being figured out and integr=
ated into UAE (partly due to its basis in 68020 and having less info on tha=
t chip) so I don't know how far they actually got with that effort usin=
g the 030 info. Perhaps it has already been 100% solved since - I don't=
know. In any case this book is probably the primary source to which we sho=
uld be referring for accuracy :)<br><br></div>D<br><br></div>
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