[eigen] question about ploadu/pstoreu and alignment

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Hi all,

I'm working on the VSX port[1][2] these days and I got stuck in
alignment issues. The particular port is for ppc64le (which is little
endian, just as arm and intel are, but contrary to the original altivec
port which is big endian). 

The issues I have are related to alignment, one is in the testsuite:

*) VSX (via vec_vsx_ld/lxvw4x intrinsic/instruction) allows unaligned
access if the offset is a multiple of 4, that is, it correctly loads a
vector from an unaligned source, in either big or little endian, but
only if alignment is multiple of 32-bits, it doesn't work otherwise. If
alignment is not multiple of 32-bits, then lxvw4x doesn't work and I
have to implement unaligned load/store via a complicated permute in the
little-endian case. Do I have to/Should I implement a generic unaligned
load that loads from arbitrary alignment? I guess I should, but I guess
I had to ask. It would definitely save me time/effort to have to worry
only for word-aligned cases.

*) the ploadu/pstoreu tests in packetmath also test the aligned case
(offset 0 in the for loop), which was how I found the above problem
actually. Are ploadu/pstoreu methods *guaranteed* to load unaligned
values, or are they supposed to work on the generic case, even if the
source/target is aligned? In case they don't then the packetmath test
has to remove the test for the zero offset. Otherwise, I would also
have to add special case in ploadu() to call pload() if alignment is
zero (I think this is redundant though and a serious performance drop).



PS. After the VSX port, I'd like to complete NEON for the new armv8, it
seems to work already but does not yet support doubles. It's definitely
going to be easier than the VSX port though.

[1]: there are actually a couple of bounties by IBM on that which I
found out after I had finished half the port :)
[2]: code in progress: https://bitbucket.org/kmargar/eigen

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